In this paper, we first present a brief review of the advanced-node logic device technology development and its key bottleneck/component processes using the existing lithographic capabilities. It is shown to be feasible to evolve into the GAA era with the minimum change of current FinFET process and a minor refining of previously reported Forksheet structure. The concept of hybrid-channel devices is raised which is not only promising for 3D vertical integration, but also offers an optimal tradeoff between device performance and power/leakage. To address the fabrication challenges, a mandrel/spacer engineering based patterning and metallization technology is proposed and its process development results are reported. This patterning & metallization technique can be applied to fabricate advanced logic and SRAM circuits with significantly enhanced pattern density. It is based on the self-aligned multiple patterning (SAMP) wherein either an alternating arrangement of different materials (with high etching selectivity) or multi-color layer decomposition (i.e., splitting of metallization process) is utilized to solve the edge-placement-error (EPE) issue. In particular, we explore various schemes of self-aligned triple patterning (SATP) to identify the potential solution to ensure a satisfactory profile control of the consecutively formed spacers. Moreover, this technique can incorporate rigorously self-aligned vias & cuts (SAVC), and accommodate a metal-layer division (MLD) to split the neighboring metal lines into two vertically staggered layers with their coupling capacitance significantly reduced. The tested metal Ru allows a direct dry etching, which offers a metal recess capability to enable an alternating-material coverage of neighboring metal wires by two different hard masks such that a selective etching can be applied to form rigorously self-aligned vias. Our early-stage process development is focused on SATP process optimization, fabrication of two simplified grating structures, material screening for appropriate etching selectivity, and metal-layer-division realization. Potential processing challenges such as Ru trench-filling quality and scaling issues of SAVC technology for advanced IC manufacturing will also be discussed.
In this paper, a general review of the past progress, current status and future perspective of MEMS/NEMS based maskless EUV digital lithography for high-resolution semiconductor manufacturing is presented. Starting from the maskless patterning resolution and throughput requirements, we shall discuss the unique characteristics of digital EUV lithography spanning from optical and system-level design, imaging methodology, writing engine, to device process development and fabrication progress achieved. The wafer scan induced image blur impacts maskless writing speed and imaging strategy. The required high demagnification and redundant multiple-pulse exposure help to enable the defect-tolerant printing. Digital EUV lithography allows multiple/sequential stitching exposures in one scanning process without throughput penalty, thus can simplify the patterning process and amplify its competitiveness in high- NA application. Moreover, its grayscale/analog imaging principle not only significantly reduces the data rate but also provides an efficient way to enhance the resolution capability. Dynamics, control and design of electrically damped MEMS/NEMS devices will be examined. A low-temperature LPCVD SiGe process for MEMS/IC integration has been developed and the micromirror fabrication results will be reviewed. It is shown that reflective nanomirrors based maskless approach is one path to cost-effective and defect-tolerant compact EUV lithography, which helps to create emerging opportunities for low-volume but cutting-edge IC applications. Potential processing challenges and scaling issues of nanomirror device technology for a timely insertion of digital EUV lithography into future advanced IC manufacturing will also be discussed.
Overlay errors, cut/block and line/space critical-dimension (CD) variations are the major sources of the edge-placement errors (EPE) in the cut/block patterning processes of complementary lithography when IC technology is scaled down to sub-10nm half pitch (HP). In this paper, we propose and discuss a modular technology to reduce the EPE effect by combining selective etching and alternating-material (dual-material) self-aligned multiple patterning (altSAMP) processes. Preliminary results of altSAMP process development and material screening experiment are reported and possible material candidates are suggested. A geometrical cut-process yield model considering the joint effect of overlay errors, cut-hole and line CD variations is developed to analyze its patterning performance. In addition to the contributions from the above three process variations, the impacts of key control parameters (such as cut-hole overhang and etching selectivity) on the patterning yield are examined. It is shown that the optimized altSAMP patterning process significantly improves the patterning yield compared with conventional SAMP processes, especially when the half pitch of device patterns is driven down to 7 nm and below.
To overcome the prohibitive barriers of edge-placement errors (EPE) in the cut/block/via step of complementary lithography, we propose a modular patterning approach by combining layout stitching, selective etching, and alternating-material self-aligned multiple patterning (altSAMP) processes. In this patterning approach, altSAMP is used to create line arrays with two materials alternatively which allow a highly selective etching process to remove one material without attacking the other, therefore more significant EPE effect can be tolerated in line-cutting step. With no need of connecting vias, the stitching process can form 2-D features by directly stitching two components of patterns together to create 2-D design freedom as well as multiple-CD/pitch capability. By adopting this novel approach, we can potentially achieve higher processing yield and more 2-D design freedom for continuous IC scaling down to 5 nm. We developed layout decomposition and synthesis algorithms for critical layers, and the fin/gate/metal layer from NSCU open cell library is used to test the proposed algorithms.
In this paper, we examine two types of 2-D layout design methodology (via connecting and direct stitching) for future IC scaling. The yield model for via landing process is first developed based on the probability-of-success (POS) function, which incorporates the overlay errors and via CD variations. A layout library is constructed using the 2-D patterns in 45-nm and 15-nm open cell libraries, and the basic stitching structures are identified. Six commonly seen stitching structures in our layout library are analyzed. The optimization methods for via landing and direct stitching are discussed. We compare the yield performance of via landing and direct stitching (with and without optimization). It is found that direct-stitching yield is better than the via-landing yield for all types of vias in the 2-D layouts we examined, regardless of whether the optimization procedure is performed.
As optical lithography and conventional transistor structure are approaching their physical limits, 3D vertical gate-all-around (GAA) nanowire MOSFETs and double-surrounding-gate (DSG) MOSFETs are two promising device candidates for post-FinFET logic scaling owing to their superior gate control and scaling potential. However, source, drain and gate of a vertical nanowire MOSFET and DSG MOSFETs are located in different physical layers. Consequently, structural design of IC devices/circuits, layout arrangement for high-density vertical nanowires/interconnects, and routing strategy are non-trivial challenges. In this paper, we shall discuss these critical issues for constructing standard cells using 3D vertical GAA nanowire MOSFETs and DSG MOSFETs. We redesigned the standard cells in Nangate Open Cell Library for 5nm node using vertical GAA nanowire MOSFETs and DSG MOSFETs. Experimental results verify the functionality of the proposed standard cell layout design approach.
In this paper, we propose a novel modular patterning technology to reduce the edge-placement errors (EPE) significantly by combining alternating-material self-aligned multiple patterning (altSAMP) and selective etching processes. It is assumed that gates and fins are fabricated by the same type of altSAMP process as mixing two different processing techniques will drive up the manufacturing costs. Process variability induced circuit performance degradation is shown to be a serious issue as FinFET devices are scaled down to sub-10nm. We analyze the dependence of FinFET-based SRAM circuit performance on supply voltage, fin-width and gate-length variations. Improved device control with narrower fins helps to increase the static noise margin (SNM) in all SRAM cell designs. Higher supply voltage is also beneficial to the SNM performance. Our simulation results show that 6-T SRAM circuit design does not meet the six-sigma yield requirement when the half pitch is scaled down to sub-7 nm. To reduce the SRAM circuit variability, we study an 8-T SRAM cell and show that it significantly improves the SRAM performance.
In this paper, we present a compact model to predict the pillar-edge-roughness (PER) effects on 3D vertical nanowire MOSFETs using the perturbation method. An analytic solution to 3D Poisson’s equation in the cylindrical coordinate with a perturbed boundary is obtained to describe the PER effects on the vertical channel potential. The induced variations of drain current, threshold voltage (Vth), and sub-threshold slope (SS) are calculated using the developed model. We also investigate the PER phase and frequency dependent behavior of the nanowire MOSFETs, and find that both phase and (angular) frequency of the PER function will significantly affect the device performance. Our model calculation results are compared with TCAD simulations and a good agreement between them is found. It is suggested that our metrology society needs to develop relevant measurement methodology to characterize the nanowire pillar-edge roughness at deep nanoscale.
In this paper, we develop statistical models to investigate SRAM yield performance and circuit variability in the presence of self-aligned multiple patterning (SAMP) process. It is assumed that SRAM fins are fabricated by a positivetone (spacer is line) self-aligned sextuple patterning (SASP) process which accommodates two types of spacers, while gates are fabricated by a more pitch-relaxed self-aligned quadruple patterning (SAQP) process which only allows one type of spacer. A number of possible inverter and SRAM structures are identified and the related circuit multi-modality is studied using the developed failure-probability and yield models. It is shown that SRAM circuit yield is significantly impacted by the multi-modality of fins’ spatial variations in a SRAM cell. The sensitivity of 6-transistor SRAM read/write failure probability to SASP process variations is calculated and the specific circuit type with the highest probability to fail in the reading/writing operation is identified. Our study suggests that the 6-transistor SRAM configuration may not be scalable to 7-nm half pitch and more robust SRAM circuit design needs to be researched.
To break through 1-D IC layout limitations, we develop computationally efficient 2-D layout decomposition and stitching techniques which combine the optical and self-aligned multiple patterning (SAMP) processes. A polynomial time algorithm is developed to decompose the target layout into two components, each containing one or multiple sets of unidirectional features that can be formed by a SAMP+cut/block process. With no need of connecting vias, the final 2-D features are formed by directly stitching two components together. This novel patterning scheme is considered as a hybrid approach as the SAMP processes offer the capability of density scaling while the stitching process creates 2-D design freedom as well as the multiple-CD/pitch capability. Its technical advantages include significant reduction of via steps and avoiding the interdigitating types of multiple patterning (for density multiplication) to improve the processing yield. The developed decomposition and synthesis algorithms are tested using 2-D layouts from NCSU open cell library. Statistical and computational characteristics of these public layout data are investigated and discussed.
In this paper, a stitch database is built from various identified stitching structures in an open-cell layout library. The corresponding stitching yield models are developed for the hybrid optical and self-aligned multiple patterning (hybrid SAMP). Based on the concept of probability-of-success (POS) function, we first develop a single-stitching yield model to quantify the effects of overlay errors and cut-hole CD variations. The overhang distance designed in a stitching process (or its mean value μ) is found to be critical to the stitching yield performance and can be optimized using this yield model. We also investigate the physical significance of several process parameters such as half pitch (HP), standard deviation (σ) of the random overhang distribution, and cut-hole CD (CL). Our study shows that certain types of stitching yield are sensitive to σ and HP, while in general high yield can be achieved for a large number of stitching types we examined. To improve the yield of certain challenging stitching structures, various layout modification strategies are proposed and discussed.
In this paper, we present a thorough investigation of self-aligned octuple patterning (SAOP) process characteristics, cost structure, integration challenges, and layout decomposition. The statistical characteristics of SAOP CD variations such as multi-modality are analyzed and contributions from various features to CDU and MTT (mean-to-target) budgets are estimated. The gap space is found to have the worst CDU+MTT performance and is used to determine the required overlay accuracy to ensure a satisfactory edge-placement yield of a cut process. Moreover, we propose a 5-mask positive-tone SAOP (pSAOP) process for memory FEOL patterning and a 3-mask negative-tone SAOP (nSAOP) process for logic BEOL patterning. The potential challenges of 2-D SAOP layout decomposition for BEOL applications are identified. Possible decomposition approaches are explored and the functionality of several developed algorithm is verified using 2-D layout examples from Open Cell Library.
A generalized edge-placement yield model for the cut-hole patterning process is developed. It incorporates the cut-hole
overlay errors, cut-hole and grating line/space CD variations into a unified physical model to investigate the key
parameters that affect the edge-placement yield. The yield related features are identified first and probability-of-failure
(POF) functions are introduced to construct the yield formula. The variable number in the yield integral is reduced from
four to two by a special transformation method. Our calculation results show that the cut-hole overhang and (grating)
line/space CD must be optimized in order to achieve the maximum yield. The sensitivity of edge-placement yield to
various statistical parameters is investigated and the overlay errors are found to play a dominant role. We also study the
scaling trend of the edge-placement yield and show that non-trivial challenges of manufacturing (half-pitch) 7-nm
FinFET devices will require significantly improved overlay accuracy and process control.
KEYWORDS: Optical lithography, Photomasks, Algorithm development, Etching, Back end of line, Logic, Amorphous silicon, Manufacturing, Front end of line, Directed self assembly
In this paper, we present a benchmarking study of directed self-assembly (DSA) and self-aligned multiple patterning (SAMP) techniques for potential applications in manufacturing 10-nm (half-pitch) IC devices. Using the self-aligned quadruple patterning (SAQP) process as an example, we compare their process characteristics and complexity/costs, identify the integration challenges, and propose various patterning solutions for both BEOL and FEOL applications.
Major differences in DSA and SAQP mask strategy, layout decomposition algorithm, and pattern-generation modeling are discussed, and critical requirements of overlay accuracy and CD control for implementing a DSA process in NAND wordline patterning are indentified. DSA technique is found to be a complementary solution for certain niche applications and we suggest that our industry should allocate more R and D resources to solve the 2-D SAMP layout decomposition challenges for logic BEOL patterning. We also propose an “out-of-the-box” idea of combining DSA and SADP process to significantly improve the 2-D design flexibility and develop a layout decomposition algorithm for this hybrid process
We present a simulation study of the near-field Extreme Ultraviolet (EUV) imaging technique to break the diffraction limit of conventional lithography for spatial frequency multiplication. Rigorous electromagnetic simulations are performed to investigate the near-field EUV imaging performance and its process capability. An optical index, depth of thickness fluctuation (DOT) is defined to characterize the tolerable variation of the imaging-layer thickness, which plays a key role in evaluating the feasibility of this lithography technology. High sensitivity of the near-field image (profile and amplitude) to both absorber CD and propagation depth is found in transverse-electric (TE) and transverse-magnetic (TM) illumination modes. Despite the attractive prospect of applying this near-field imaging technique for semiconductor manufacturing, technical challenges from its optical performance and process control are non-trivial.
In this paper, a generalized model to predict fin-width roughness (FWR) induced FinFET device variability is developed using the boundary perturbation method. An analytic solution to Poisson’s equation with a perturbed boundary is derived to describe the FWR effects on the sub-threshold electric potential and drain current. High model accuracy under various device operating conditions is demonstrated by a detailed comparison with TCAD simulations. The correlation among the threshold-voltage shift, dominant fin-roughness frequency, and phase difference (between two dominant fin-edge roughness functions) is identified. It is found that a periodic fluctuation of the threshold voltage can be induced by the phase difference, while more significant variations are observed at lower frequencies. Our study also shows that thinner gate oxide and wider fins will help to reduce the FWR effects.
Self-aligned multiple patterning (SAMP) is a promising technology to scale IC devices to 7-nm half pitch and several 3- mask negative-tone SAMP processes for 2-D BEOL patterning applications have been proposed recently. In this paper, the existing coloring rules in self-aligned quadruple and sextuple patterning (SAQP and SASP) processes are reexamined first. We further discuss the geometric relation between various features and remove the unnecessary constraints, and develop improved layout decomposition algorithms for both processes. The cut-mask related overlay issue is addressed by proposing an edge-expansion solution when generating the cut patterns. Finally, we show that numerous standard M1 cells in the Open Cell Library, when slightly modified, can be successfully decomposed. This verifies the functionality of the new decomposition algorithms for continuous logic scaling to deep nano-scale using SAMP techniques.
Self-aligned multiple patterning (SAMP) techniques can potentially scale integrated circuits down to half-pitch 7nm. In this paper, we present a comparative analysis of self-aligned quadruple (SAQP) and sextuple (SASP) techniques by investigating their technological merits and limitations, process complexity and cost structures, strategy of layout decomposition/synthesis, and yield impacts. It is shown that SASP process complexity is comparable to that of SAQP process, while it offers 50% gain in feature density and may be extended for one more node. The overlay yield of cut process is identified to be a challenge when the minimum device feature is scaled to half-pitch 7nm. The mask design issues for various applications using each technique are discussed, and the corresponding layout decomposition/synthesis strategy for complex 2D patterning is proposed. Although the high-dose EUV single-cut process can save significant costs when applied to replace the 193i multiple-cut process to form fin/gate structures, our cost modeling results show that SADP+EUV approach is still not cost effective for patterning other critical layers that generally require the same mask number (and lithographic steps) as the non-EUV schemes.
The impacts of self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) process variability on SRAM circuit performance are studied in this paper. Different types of SRAM circuit variability such as intra-cell and inter-cell variability are discussed. Spatially periodic variation patterns of a SRAM array fabricated with SATP process is identified, while spatial variation of SAQP based SRAM array is found to be less significant. Statistical TCAD simulations are carried out to examine the process variability induced fluctuation of SRAM circuit performance. It is found that SRAM static noise margin (SNM) shrinks with increased variations in line-width roughness and CD, especially when the technology node is scaled down. Despite the SATP/SAQP process variability and the related SNM reduction, our simulations show that the induced fluctuation of SRAM circuits is still manageable. It is also confirmed that circuit stability and manufacturing yield of SAQP based SRAM are better than SATP based SRAM.
In this paper, we present a cut-process overlay yield model for self-aligned multiple patterning and study how its yield will be affected by the overlay errors and cut-hole overhang. A geometric model is developed to identify the yield-related structures and construct the probability-of-failure (POF) functions. A general formula to calculate the cut-process overlay yield is derived using the joint POF function. Our calculation results show that an optimal cut-hole overhang must be found in order to achieve the maximum yield. The scaling tendency of the cut-process overlay yield is also studied, and it is found to be a potential challenge when the half pitch of device features reaches 7nm. The yields of 4-mask 193i and single-mask EUV cut modules are also calculated for a comparison. Moreover, a post-lithography misalignment correction technique based on dry etching is proposed. A geometric tilted etching model is developed to predict the relation between the tilting angle of an etching process and the shifted distance of the etched structure’s mass center.
Self-aligned quadruple patterning (SAQP) process is a proven technique for deep nano-scale IC manufacturing, while its mask design and layout decomposition strategy is less intuitive. In this paper, we examine both 2- and 3-mask SAQP process characteristics and develop various decomposition methods to achieve higher feature density and 2-D design flexibility. It is demonstrated that by generating assisting mandrels, SAQP layout decomposition can be degenerated into a SADP decomposition problem for which mature algorithms already exist in our EDA industry. Moreover, a spacer-expansion mask concept is introduced and a grouping/coloring algorithm to assign feature colors is developed for 3-mask SAQP layout decomposition. Finally, several 2-D layouts are successfully decomposed, showing the functionality of the decomposition method we proposed.
Self-aligned sextuple patterning (SASP) is a promising technique to scale down the half pitch of IC features to sub- 10nm region. In this paper, the process characteristics and decomposition methods of both positive-tone (pSASP) and negative-tone SASP (nSASP) techniques are discussed, and a variety of decomposition rules are studied. By using a node-grouping method, nSASP layout conflicting graph can be significantly simplified. Graph searching and coloring algorithm is developed for feature/color assignment. We demonstrate that by generating assisting mandrels, nSASP layout decomposition can be degenerated into an nSADP decomposition problem. The proposed decomposition algorithm is successfully verified with several commonly used 2-D layout examples.
A compact model is developed to study the fin-width roughness (FWR) induced device variability and its impacts on FinFET performance. The perturbation theory is applied to obtain the analytic solution to nonlinear Poisson’s equation by treating FWR as a small deviation/perturbation from the ideal (flat) fin boundary. High accuracy of this compact model is verified with TCAD simulations. Both model calculation and TCAD simulation results show that FWR variation significantly affects FinFET device behavior. The conventional short-channel model is inaccurate to describe the FWR effects. Several types of FWR functions are studied and important device parameters such as Vt.sat, Vt.lin, DIBL are extracted from TCAD simulations, all of which are found sensitive to FWR variation.
In this paper, we present the research progress made in maskless EUV lithography and discuss the emerging
opportunities for this disruptive technology. It will be shown nanomirrors based maskless approach is one path to costeffective
and defect-free EUV lithography, rather than making it even more complicated. The focus of our work is to
optimize the existing vertical comb process and scale down the mirror size from several microns to sub-micron regime.
The nanomirror device scaling, system configuration, and design issues will be addressed. We also report our theoretical
and simulation study of reflective EUV nanomirror based imaging behavior. Dense line/space patterns are formed with
an EUV nanomirror array by assigning a phase shift of π to neighboring nanomirrors. Our simulation results show that
phase/intensity imbalance is an inherent characteristic of maskless EUV lithography while it only poses a manageable
challenge to CD control and process window. The wafer scan and EUV laser jitter induced image blur phenomenon is
discussed and a blurred imaging theory is constructed. This blur effect is found to degrade the image contrast at a level
that mainly depends on the wafer scan speed.
Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for
scaling integrated circuits down to sub-15nm half pitch. By implementation of active layout decomposition/synthesis
using mandrel and spacer engineering, SATP process represents a prospective trend that not only drives up the feature
density, but also breaks the 1-D gridded limitations posed to future device design. In this paper, we shall present the
research progress made in optimizing SATP process to improve its lithographic performance. To solve the previously
reported difficulties in etching small mandrels and removing sacrificial spacers, new materials are tested and a
promising scheme (using oxide as the mandrel and poly/amorphous Si as the sacrificial spacer) is identified. In the new
process, a diluted HF process is applied to shrink the mandrel (oxide) line CD and a highly selective dry etch (which
does not attack the mandrel and structural spacer) is developed to strip the sacrificial Si spacers, resulting in
significantly improved process performance. We also address the issue of reducing SATP process complexity by exploring the feasibility of a 2-mask concept for specific types of layout.
A hybrid self-aligned triple and negative-tone double patterning (HTDP) technique is proposed to achieve improved
resolution and quasi-2D IC design flexibility at lower cost. Critical challenges of HTDP process and its key design
issues such as overlay, layout decomposition and synthesis are investigated, and possible design solutions are discussed.
It is shown that using mandrel (including assisting mandrel) and spacer engineering, HTDP on-grid layout design is a
promising approach to break the limitation of 1-D gridded design. Efficient formulation of HTDP layout
decomposition/synthesis into a Boolean satisfactory problem is demonstrated. Moreover, by considering geometric
constraints of HTDP layout and several process related assumptions, it is possible to significantly reduce the number of layout features and Boolean input variables. Several examples of 2-D layout are used to demonstrate the process of HTDP decomposition/synthesis, as well as the simplification of its algorithm to reduce runtime. Specifically, preliminary results from implementation of a 2-mask HTDP design for patterning a 2-D dense line/space array with pads are reported.
As promising paths to break the diffraction limit of optical lithography, several self-aligned multiple patterning (SAMP)
techniques have been proposed to improve the resolution capability recently. In this paper, we show that SATP (selfaligned
triple patterning) process variations differ significantly from conventional optical lithography process. It is
found that mandrels fabricated by a SATP process usually come up with worse line-width roughness (LWR) and
critical-dimension uniformity (CDU) than spacers do. In addition to that, the gap space between two neighboring
spacers is often accompanied with a poor CDU. Similar to SATP process, the self-aligned quadruple patterning (SAQP) technique also brings its own characteristics of process variability along with the scaling capability. SAMP process variability (such as intra-cell variability and process multi-modality) and their impacts on device performance of the multiple-gate MOSFETs are discussed. Moreover, we develop an analytic double-gate MOSFET model to study the effects of LWR on both fin thickness and gate misalignment. Numerical simulations are carried out to verify the accuracy of our simplified model. This analytic approach provides an efficient method for compact modeling of LWR induced device variations.
Spacer based self-aligned multiple patterning (SAMP) techniques potentially allow us to scale integrated circuits down
to sub-10nm half pitch with no need of EUV lithography. In this paper, we shall present a general analysis of
technological merits, process complexity and costs of various SAMP techniques. It is shown that some SAMP
techniques such as self-aligned quadruple/sextuple patterning (SAQP/SASP) are more capable of increasing the pattern
density, while self-aligned triple patterning (SATP) is more beneficial to reducing process complexity by allowing
quasi-2D IC design and requiring fewer masks. Besides their different scaling/resolution capability and process
challenges, each SAMP technique is accompanied with unique characteristics of CD uniformity (CDU) and line-width
roughness (LWR), which indicates their application areas and the related IC design/fabrication methodologies vary
significantly by industry segment. Process costs of various self-aligned multiple patterning schemes are calculated,
which show that within the common resolution capability, SATP technique is the most cost effective while the
EUV+SADP approach only offers limited benefits.
Novel patterning approaches are explored to enable either more cost-effective manufacturing solutions or a potential
paradigm shift in patterning technology. First, a simplified self-aligned quadruple patterning (SAQP) process is
developed to extend 193nm immersion lithography to half-pitch 10nm patterning. A detailed comparison with other
SAQP schemes is made, and we find the simplified SAQP process can significantly reduce process complexity and
costs. On the other hand, the topographic effect on the spacer width causes difficulty in obtaining lines with equal CD,
thus a CVD/etch solution must be searched to meet the CDU requirement.
Moreover, a motion-induced frequency multiplication (MIFEM) concept is proposed; and specifically, we develop a
stress-induced frequency multiplication (SIFEM) technique to produce half-pitch 9nm lines/spaces with no need of ebeam,
imprint, or self-assembly technology. It allows us to apply standard semiconductor fabrication processes and
equipment to drive down the half pitch of a spatially periodic pattern below 10nm. The resolution of this patterning
technique is dependent on the CD of spacers and their gaps regardless of optical resolution of the lithographic tool. The
final space CD is mainly related with the material property of the fluid used in SIFEM process. The main issues of
SIFEM process include: adjusting the fluid property to tune the gap CD, designing the anchor structures and line route
to control the strength and direction of film stress, and overlay methodology development, etc.
KEYWORDS: Etching, Double patterning technology, Oxides, Lithography, Photomasks, Optical lithography, Back end of line, 193nm lithography, Image processing, Front end of line
In this paper, a recessive self-aligned double patterning (RSADP) process enabled by gap-fill technology is
proposed and developed for BEOL applications. FEOL application is also possible by adding gap-fill/CMP steps
to reverse the tone of contact/trench patterns. Compared with positive-tone spacer self-aligned double patterning
(SADP), RSADP technique can reduce the process complexity by using less masks to pattern 2-D features. With a
RSADP process, we successfully demonstrate (half-pitch) 50nm contact and 30nm line/space patterns using dry
lithography.
A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm
patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned
double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling
candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical
layers and reduce their process complexity by using less masks.
A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer
patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain
lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If
applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology
of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns
with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line
width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major
focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different
materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key
requirements (e.g., LER and CDU) of the lithographic performance.
In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of
using lithography as the principal process for generating device features, the role of lithography becomes to generate a
mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density
multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to
the scaling roadmap as the exposure tools themselves.
Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash
where layouts were simple and design space was focused. But today, the use of advanced automated decomposition
tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the
use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple
patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating
polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails
formed onto the substrate.
In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various
forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple
patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of
addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning
design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL
routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of
EUV+SADP.
193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its
patterning capability to about 20nm using the double-patterning technique[1]. Despite the non-trivial sub-20nm
patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology.
25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm
NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall
spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm
pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and
demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements.
In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including
300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for
sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical
dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our
VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables
accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer
quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath
amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.
Chemical shrink and SAFIER are two resist shrinking processes that have been proved effective to reduce the trench
and contact hole CD with enhanced resolution and process windows. Patterning sub-20 nm trenches, however, is found
to be challenging using a single shrink process. To shrink resist trenches from 40-60 nm to sub-20 nm, a double shrink
process seems more promising and we have studied the double chemical shrink, double SAFIER, and other possibilities.
It is found that SAFIER process is capable of shrinking trenches by more than 30 nm with improved LER, but it suffers
from severe CD non-uniformity (e.g., much smaller trenches at wafer center) induced by high SAFIER bake
temperature applied to resists to obtain large shrinkage. Chemical shrink can also result in a fairly large shrinkage at
high bake temperature, but LER is poor with no improvement in CDU. A novel hybrid process to combine chemical
shrink (first) and SAFIER (last) together is proposed and developed. We find that this hybrid approach avoids the
disadvantages of two mentioned shrinking processes and has the capability of patterning sub-20 nm trenches in resists
with manufacturable process window, CDU and LER. Oxide and nitride etching process with APF (Advanced
Patterning Film) as a hard mask is developed and sub-20 nm oxide/nitride trench patterning with excellent LER and
acceptable CDU is achieved. APF hard mask is found to significantly improve CDU and LER of small trenches. Relations between CD/shrinkage and process temperature, pitch, and mask trench CD are investigated and the experimental results will be presented in this paper.
KEYWORDS: Principal component analysis, Simulation of CCA and DLA aggregates, Matrices, Critical dimension metrology, Semiconductor manufacturing, Canonical correlation analysis, Stochastic processes, Statistical analysis, Data processing, Statistical methods
A general predictive method based on Canonical Correlation Analysis (CCA) is developed to
identify globally correlated process modes that are responsible for the spatial variability in deep
nanoscale semiconductor manufacturing. This multivariate statistical method overcomes the
limitations of ordinary multiple linear regression technique by introducing canonical variates with
certain properties which allow us to construct a transfer matrix to relate the predictand vector to the
predictor vector directly. Principal Component Analysis (PCA), another multivariate statistical
technique, is introduced to find the orthogonal modes that explain the larger fraction of the total
process variations. We also discuss the constraint of sample number in CCA and propose using the
leading principal components (PCAs) to replace the original raw data in correlation analysis.
In this paper we present analytical and simulation results on the wafer-scan induced image blur and its impact on CD control, image slope and line-edge roughness (LER), and process window in maskless lithography. It is shown that the effects of image blur do not impose serious constraints on lithographic performance in low throughput operation. However, when throughput is high, significant CD enlargement, lower image slope and higher LER, and process window degradation are observed consistently in both coherent imaging analysis and partially coherent lithographic simulations. The dependence of CDs on the wafer's scan speed and the distance between neighboring features will be an important issue of maskless OPC development. We also analyze the potential challenges of image blur to DUV and EUV maskless lithography and propose several solutions to overcome them.
In this paper we present the design and fabrication results of tilting and piston micromirrors for their potential applications in DUV and EUV maskless lithography. The dynamic characteristics such as stability, damping, and the settling time of various types of electro-mechanically coupled micromirrors are investigated using the perturbation method, linear control theory, and numerical simulation. Non-dimensional control parameters are identified and transient optimization is carried out to minimize the systems’ settling time. It is found that vertical double-comb tilting micromirrors and clamped double-flexure piston micromirrors have superior stability.
The mirror hinge is proposed to function as a built-in resistor to introduce optimal electrical damping for EUV micromirrors operating in vacuum. We have developed a low-temperature (<420°C) IC compatible SiGe process, in which SiGe can be doped at different levels without annealing to function as a structural (conductive) and damping (resistive) material. Self-aligned processes using "spacer nanolithography" to define ultra-thin nano-scale actuation gaps for low-voltage operation have been developed to fabricate both tilting and piston micromirrors. We have successfully constructed double-comb tilting micromirrors with 300-nm fingers and 40-nm finger gaps, and double-flexure piston micromirrors with 80-nm thick flexures and 80-nm actuation gaps. The mirror sizes are in the range of 10 to 0.5 mm.
This paper discusses image optimization challenges posed by a mirror based pattern generation scheme. We address defocus related image drift encountered with mirror based maskless lithography. While off-grid contacts printed with piston mirrors are most severely affected most other features can be printed with minimum loss of telecentricity. A novel double-piston mirror architecture based on a combination of tilting and piston mirrors is introduced. It operates as a pseudo-tilt mirror but also has the advantage of allowing strong phase-edges due to pure-phase wavefront modulation. Exposure latitude versus depth-of-focus process window curves of typical features show that the new mirror design behaves as well as tilting mirror. An image optimization algorithm is presented that iteratively updates the mirror array phase-map to optimally print dense layout, accounting for inter and intra feature proximity effects.
We study mirror based pattern generation systems to provide an understanding of how they can be operated in an analog mode to meet the quasi-continuous sizing and placement requirements of optical lithography. Both tilting mirrors and piston-motion mirrors are examined. The aerial images are compared with those generated by simple binary masks. The effect of grayscaling, used to place and size features, on image quality is measured. Normalized image log slope (NILS) is used as the measure of image quality. Tilting mirrors used in grayscale mode provide image quality comparable to binary masks, and piston mirrors are somewhat better.
A novel shape design of the comb drive to achieve digital switches while avoiding the unstable pull-in is presented. The statics and dynamics of switching are discussed and the voltage- displacement-transfer characteristic is demonstrated. The degradation of the transfer characteristic can be caused by either the overshoot of actuators in the transient switching or the actuator geometry. An optimal design of the actuator geometry is proposed to improve the quality of the transfer characteristic. On the other hand, the settling time of the comb drive's transient response to a step excitation will be minimized for high-speed switches. To achieve this, two non-dimensional control parameters are identified and physically interpreted. Then a transient optimization is carried out by introducing an optimal electrical damping and choosing a zero static comb overlap. The optimal transient response is obtained by analytically solving the linearized force/moment and electric equations. Finally numerical simulation is performed to verify the analytic solution and extend the analysis to the nonlinear regime.
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