Field-effect transistors (FETs) with channels of two-dimensional transition metal dichalcogenides (2D TMDs) are expected to extend Moore’s law by extreme scaling of contacted gate pitch (CGP) post silicon-sheet-based complementary FET (CFET) devices. The ultrathin body and fully passivated surface of 2D materials result in superior electrostatic control and improved short channel behavior. Challenges such as high contact resistance or lack of doping technology are on the way of 2D-FETs reaching the required performance for high-performance logic applications. Additionally, in order to integrate 2D TMDs in ultra-scaled CMOS devices, developing a patterning scheme via the state-of-the-art extreme ultraviolet (EUV) lithography is essential. In this paper we demonstrate our first results on studying the compatibility and interaction of semiconducting 2D TMDs with EUV environment using a set of characterization techniques that are fit to detect qualitative defects and morphological changes in these atomically thin layers. Our study is focused on semiconducting TMDs that are currently the most promising candidates for transistor channels: MoS2 (NMOS) and WSe2 (PMOS). We report the interaction of EUV photons and photo-electrons with blanket films of MoS2 and WSe2 for different EUV doses in vacuum environment. Based on the current findings we propose design of experiments aiming at developing controllable and tunable modification and patterning of 2D TMDs with the EUV energy and resolution for advanced device nodes.
A pattern-based methodology for optimizing Self-Aligned Double Patterning (SADP)-compliant layout designs is developed based on detecting cut-induced hotspot patterns and replacing them with pre-characterized fixing solutions. A pattern library with predetermined fixing solutions is built. A pattern-based engine searches for matching patterns in the layout designs. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution, preserving only the design rule check-clean replacements. The methodology is demonstrated on a 10nm routed block. A small library of fourteen patterns reduced the number of cut-induced design rule check violations by 100% and lithography hotspots by 23%.
Printing contact-like cut mask form the line end of very dense pitches is imposing a significant challenge to lithography. Various lithography options including optical multi-patterning and EUV have been considered for sub-20nm half pitch metal line cut process. Different lithography solutions of cut mask will impose different design restrictions and thus lead to different scalability of chip. In this paper, we will study routing limitations of sub-20nm half pitch metal lines cut with various optical and EUV lithography options. Key metal routing rules for each cut mask option will be derived based on study of forbidden cut mask configurations. The associated logic area impact will be derived based on real digital design.
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