In this study, influence of geometric features of phase defect on EUV optical images, such as dark field images(ABI tool) and bright field images (Exposure tool), was studied with experiment and simulation. It is confirmed that ABI signal intensity has a direct relationship not only with defect volume but also with geometric features of the phase defect. A new method for the making of phase defect models for simulation purpose was attempted. With this new method, the simulated ABI signal intensity exhibited a good proportionality relationship with the experimentally obtained ABI signal intensity. This method is believed to be effective in the estimation of ABI signal intensity with simulation. These results lead to the conclusion that it is important to take into consideration the geometric features of phase defects when a relationship between ABI signal intensity and phase defect feature is to be examined. Also, the relationship between ABI signal intensity and impact of defect on wafer was studied with simulation. In this study, many geometric types of phase defects were used, and relationships between these defects and their impacts on
wafers were studied. As a result, it was confirmed that the geometric features did not strongly affect the relationship between the ABI signal intensity and the defects’ impacts on wafer however the ABI signal intensity is found to have a close relationship with impact of defect on wafer. These results lead to the conclusion that information about ABI signal intensity is important not only for the detection of phase defect but also for estimating the impact of phase defects on wafers.
The influence of surface roughness of an EUV mask on wafer image has been thoroughly investigated by lithography
simulation with the Monte Carlo method. Based on the power spectral density of the surface roughness of an actual mask,
and based on a given random phase distribution, we have reconstructed a number of rough surfaces with various rms
roughness values. We quantitatively estimated the impacts of these reconstructed rough surfaces on wafer images.
Furthermore, we also investigated the influence of phase defects formed on the rough surfaces. We then did the process
margin analysis that showed the specifications of the surface roughness.
In this paper, phase defect impact variation, which is caused by the characteristics of defect shapes, is verified by a
simulation. Actinic blank inspection (ABI) signal intensity, and defect image intensity on wafer, affected by characteristics changes in the shape of the phase defect, was calculated. ABI signal intensity and defect image intensity on wafer did not remain constant even when the phase defect volume was fixed. According to this simulated result, defect side wall angle and defect volume (with tilted top surface) affected both intensities. When the impacts, caused by phase defect, on ABI signal intensity, and on defect image intensity on wafer, are monitored then shape of the phase defect should be taken into consideration for accurate estimation. Also, through this simulation, a relationship between ABI signal intensity and defect image intensity on wafer was confirmed. The impact variation (which is caused by defect shape change) for both intensities showed similar tendencies. Therefore, it is believed that ABI system is an effective way to capture harmful phase defects affecting the wafer intensity, even when there were defects with various shapes.
In extreme ultraviolet lithography, reducing the number of phase defects (PDs) on mask blanks is a critical issue because the PDs cause degradation of the printed pattern quality. To minimize the number of printable PDs, covering PDs beneath an absorber pattern is an effective way of addressing the problem. Therefore it becomes necessary to detect the PDs and pinpoint their locations by a blank inspector. In this work, a three-dimensional analysis of PDs has revealed that some PDs can grow and propagate in an angular direction away from the normal to the substrate surface. The impact of the inclination angle on the printing performance was evaluated by calculating printed pattern images using a simulator. A PD with an inclination angle of 1 deg corresponds to a 1-nanometer positional shift compared with a position defined as surface topography of a defect as observed by an atomic force microscope or by some nonactinic defect inspector. However, an actinic blank inspection (ABI) tool with high-magnification optics can pinpoint the actual location of the PDs. Covering a PD under an absorber pattern, by a shifting of the pattern based on the information of the PD’s location obtained by the ABI tool, works quite well.
Phase defect printability and imaging characteristics were investigated by using aerial image simulation to clarify the
phase defect impact on patterns depending on defect types, and on exposure conditions. In particular, the difference
between the impacts caused by the same size bump phase defect and pit phase defect on 28 nm ~ 16 nm L&S projected
patterns were investigated by calculating line width variations. Aerial images of phase defects in an absence of any
absorber pattern were also calculated, and the image intensity losses of the two types of defects were compared. For a
dipole illumination with 0.25 NA (numerical aperture) the pit phase defect impact was found to be stronger than the
bump phase defect impact, when the two defect widths were less than 70% of the half-pitch of L&S patterns on the mask.
This occurrence was not foreseen by the defect image calculation. On the other hand, for circular illumination with 0.33
NA, the bump defect impact was found to be stronger than the pit phase defect impact, which was consistent with the
defect image calculation results. The contribution of dipole illumination in lowering the phase defect impact was
confirmed for both bump and pit phase defects.
A variety of phase defects (PDs) such as programmed bump and pit PDs, and native bump and pit PDs were detected by
a dark-field ABI (Actinic Blank Inspection) tool. Among the PDs, some of them seemed to grow and propagate in an
angular direction, away from substrate surface as was found by a TEM analysis. This presentation reports on the
influence of 3-D phase defect on wafer printability, and on defect detection signals of an ABI tool. The result shows that
the impact of the inclination angle on printing performance was quite significant when the PDs were not covered with
the absorber pattern. On the other hand, the defect detection signal intensity was negligibly small in the case where the
inclination angle was less than 9 degrees. However, ABI with its high magnification optics can pinpoint the PD's actual
location as defined by the EUV light, rather than the ones that are not so clearly define by the surface topography.
In this work, a simulation for actinic dark-field inspection with amplitude defects was carried out. The simulation was then
followed by experiments on actinic dark-field inspection with programmed amplitude defects. For this experiment, the
programmed amplitude defects were fabricated using EB exposure.
The simulated result showed that the intensity signal was influenced by the thickness and width of the amplitude defect.
The simulated results were then confirmed by the experiments. The tendency of the result was approximately similar to the
simulated results. However, the dependency on the two factors of defect thickness and defect width is not similar to the
simulated results. As the factors of difference, difference of defect edge angle and element of defect model expected.
This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond
replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction.
The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since
sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional
illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination.
Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in
SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics
was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the
point spread function of the projection optics. This means that the established concept of flare correction is usable with
advanced optics.
When a thinner absorber mask is applied to extreme ultraviolet (EUV) lithography for chip production, it becomes essential to a introduce light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. In this paper, we evaluate the leakage of both EUV and out-of-band from light-shield border and clarify the dependence of lithographic performance on light-shield border structure using a small field exposure tool with/without spectral purify filter (SPF). Then we evaluate the lithographic performance of a thin absorber EUV mask with light-shield border of the etched multilayer type and demonstrate the merit of its structure using a full-field scanner operating under the currently employed condition of EUV source in which SPF is not installed.
The impact of an EUV mask absorber defect with pattern roughness on lithographic images was studied. In order to reduce systematic line width roughness (LWR) of wafer printed patterns, the mask making process was improved; and in order to reduce random LWR, low line-edge roughness resist material and a critical dimension averaging method of multiple-exposure shots were introduced. Then, by using a small field exposure tool, a mask-induced systematic printed LWR was quantified and estimated at 32-nm half-pitch and 28-nm half-pitch. The measurement results of the critical mask absorber defect size were compared with the simulation, and the results were then discussed.
We are focusing on the establishment of a flare correction technique for half pitch (HP) 22-nm generation in Extreme
Ultra Violet Lithography (EUVL). However, there are some difficulties in the areas of flare calculation and edge biasing,
associated with flare correction because of the tighter CD control requirements. In our previous work, we investigated
the feasibility of an improved flare calculation and a new way of edge biasing. For the flare calculation, we adopted a
short-range flare kernel method, which calculates short-range flare using a fine mesh only at the edges of patterns that
require correction. From the simulation and experimental results of this method, we confirmed that it can calculate flare
value accurately in a reasonable runtime. On the other hand, since the edge biasing has pattern dependency the work has
to be customized accordingly, and that can lead to labor intensive task of pattern-dependent biasing. To address this
problem, we began to explore the usefulness of model-based flare correction that has been improved where it can
modulate the aerial image according to the flare effect during model-based OPC.
For this work, we prepared a test mask containing line-and-space (L/S) patterns of several pitches with different flare
levels. We then evaluated the accuracy of the model-based flare correction by simulating the corrected L/S patterns using
a rigorous lithography simulation with 3-D mask stack structure. As a result, the CD error range was found to be from - 1.56 to 1.12 nm, which is within ±2 nm (±10 % of the minimum target CD). It is thus concluded that the model-based
flare correction can deliver high accuracy results even where OPCs are also involved.
When a thinner absorber mask is applied to EUVL for ULSI chip production, it becomes essential to introduce EUV
light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. Thin absorber mask
with light-shield border of etched multilayer adds to the process flexibility of a mask with high CD accuracy. In this
paper, we demonstrate the lithographic performance of a thin absorber mask with light-shield border of etched
multilayer using a full-field exposure tool (EUV1) operating under the current working condition of EUV source.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
Impact of EUV mask absorber defect with pattern-roughness on lithographic images was studied. In order to reduce
systematic line width roughness (LWR) of wafer printed pattern, mask making process was improved; and in order to
reduce random LWR, low line edge roughness (LER) resist material and a CD averaging method of multiple exposure
shots were introduced. Then by using a Small Field Exposure Tool (SFET), mask induced systematic printed LWR was
quantified and estimated at 32nm HP and 28nm HP. The measurement results of the critical mask absorber defect size
were compared with simulation; and the results are then discussed.
Extreme ultraviolet lithography (EUVL) is one of the most promising candidates for the next-generation lithography. For
the adoption of EUVL, however, there are some technological issues to be solved. One of the critical issues is flare
which is an undesirable scattered light that reduces the aerial image contrast leading to a reduction in the process window
such as exposure latitude. Therefore, new methods to compensate for the anticipated flare effect have to be devised.
At Selete, flare correction based on a flare point-spread function (PSF) is investigated. We succeeded in achieving a CD
control of within a few nm over various pattern densities for the half-pitch (HP) 32-nm node.
However, our estimation shows that the previous flare correction scheme could not meet the accuracy criteria of flare
computation for HP 22-nm node. Therefore, we have modified the flare correction flow to implement a variable gridding
for pattern-density calculation. The variable gridding based on the shape of a PSF enables highly accurate flare
calculation within a reasonable runtime.
Furthermore, we will use model-based OPC for HP 22-nm node, whereas we normally use rule-based OPC for HP 32-
nm node. This is because the lithography process is reaching the low k1 regime.
In this work, we investigate the feasibility of model-based OPC incorporating flare correction.
This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
In this paper, we will report on our experimental results on the impact of inspection system optics on mask defect
detection sensitivity. We evaluated the capability of detecting defects on the EUVL masks by using a new inspection
tool (NPI6000EUVα) made by NuFlare Technology, Inc. (NFT) and Advanced Mask Inspection Technology, Inc.
(AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect inspection system using 199nm
wavelength inspection optics. The programmed defect mask with LR-TaBN absorber was used which had various sized
opaque and clear extension defects on hp-180nm, hp-128nm, and hp-108nm line and space patterns. According to the
analysis, to obtain optimum sensitivity for various types of defects, using both C- and P-polarized illumination
conditions were found to be effective. At present, sufficient defect-detection sensitivity is achieved for opaque and clear
extension defects in hp128nm (hp32nm at wafer). For hp108nm (hp27nm at wafer), using both C- and P- polarized
illumination is effective. However, further developments in defect-detection sensitivity are necessary.
In this paper, we will report on our experimental and simulation results on the impact of EUVL mask absorber
structure and of inspection system optics on mask defect detection sensitivity. We employed a commercial simulator
EM-Suite (Panoramic Technology, Inc.) which calculated rigorously using FDTD (Finite-difference time-domain)
method. By using various optical constants of absorber stacks, we calculated image contrasts and defect image signals as
obtained from the mask defect inspection system. We evaluated the image contrast and the capability of detecting
defects on the EUVL masks by using a new inspection tool made by NuFlare Technology, Inc. (NFT) and Advanced
Mask Inspection Technology, Inc. (AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect
inspection system using 199nm wavelength inspection optics. The programmed defect masks with LR-TaBN and LRTaSi
absorbers were used which had various sized opaque and clear extension defects on hp-160nm, hp-225nm, and hp-
325nm line and space patterns. According to the analysis, reflectivity of EUVL mask absorber structures and the
inspection optics have large influence on image contrast and defect sensitivity. It is very important to optimize absorber
structure and inspection optics for the development of EUVL mask inspection technology, and for the improvement of
performance of EUV lithographic systems.
At Selete, correction for flare based on a flare point-spread function (PSFF) is investigated. We divide a layout into a grid
and calculate pattern density for each grid square, obtaining a density array as an approximation to the layout aerial
image. Then, the density array is convolved with the PSFF to create an array of flare values. Using this flare-value array,
we resize the layout.
In the above correction flow, size of a grid square of density array and a selection of an approximate function of the PSFF
have a great influence on the accuracy of flare value computation.
In this study, correction for flare was applied to the fabrication of several test masks using the real PSFF obtained from a
full-field step-and-scan exposure tool called EUV1. We report on the optimization of size of grid square, on a suitable
approximation model of PSFF, and on feedbacks from exposure experiments.
The effect of mask absorber thickness on defect printability in EUV lithography was studied. In case of very thin
absorber, when used for EUVL mask, it became necessary to set specifications for mask defects for the
manufacturability of ULSI devices because mask absorber thickness could impact defect printability. We prepared
programmed mask defects of LR-TaBN absorber with various thicknesses. We then investigated defect printability of
thin absorber mask with Small Field Exposure Tool (SFET) by comparing the data with simulation results.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on
accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in
these areas. The overall lithography performance was determined from the performance of the exposure tool, the
printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction
technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33
mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus,
the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation
of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on
CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the
projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an
electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal
wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of
EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten
wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were
found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We
found the PL test site to be very useful for determining where further improvements need to be made and for evaluating
the production readiness of EUVL.
In this paper, we will report on our experimental and simulation results on the impact of EUVL mask absorber
structure and of inspection system optics on mask defect detection sensitivity. We employed a commercial simulator
EM-Suite (Panoramic Technology, Inc.) which calculated rigorously using FDTD (Finite-difference time-domain)
method. By using various optical constants of absorber stacks, we calculated image contrasts and defect image signals as
obtained from the mask defect inspection system. We evaluated the image contrast and the capability of detecting
defects on the EUVL masks by using a new inspection tool made by NuFlare Technology, Inc. (NFT) and Advanced
Mask Inspection Technology, Inc. (AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect
inspection system using 199nm wavelength inspection optics. The programmed defect masks with LR-TaBN and LRTaSi
absorbers were used which had various sized opaque and clear extension defects on hp-160nm, hp-225nm, and hp-
325nm line and space patterns. According to the analysis, reflectivity of EUVL mask absorber structures and the
inspection optics have large influence on image contrast and defect sensitivity. It is very important to optimize absorber
structure and inspection optics for the development of EUVL mask inspection technology, and for the improvement of
performance of EUV lithographic systems.
Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal
with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with
proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist
performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be
6.1% or 6.6%, as calculated from the residual part of the low- or middle-frequency region, respectively. The flare level
was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from
the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch
patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a
σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask
CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD,
we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD
mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance
up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In
a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled
off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that
aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results
yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This
research was supported in part by NEDO.
We propose a new method of quality assurance for attenuated phase shifting mask (PSM) using the concept of the flexible mask specifications to extend the life of PSM [1]. The haze on PSM is a major issue for ArF lithography in semiconductor device manufacturing since it causes decline of device yield. PSM irradiated by ArF laser is periodically cleaned before haze is printed on wafer, which is a killer defect. Repetition of cleaning causes great changes of properties, i.e. phase, transmittance. Therefore, the number of times cleaning is performed has been limited by predetermined specifications based on ITRS. In this paper, relaxation of the pass/ fail criteria are studied as one solution to this limitation problem. In order to decide a suitable number of times for cleaning to be performed, we introduce the concept of flexible mask specifications, taking lithography margin into account.
Firstly, we obtained mask parameters before cleaning; these parameters were, for instance, phase, transmittance and CD. Secondly, using these parameters, we simulated images of resist pattern exposed on wafer and obtained exposure latitude at desired depth of focus. Thirdly, we simulated mask parameters and exposure latitude when the mask was cleaned several times and obtained correlation between number of times cleaning is performed and exposure latitude. And finally, we estimated suitable pass/ fail criteria of mask parameters and the maximum number of times cleaning should be performed for each mask at the standard exposure latitude. In the above procedure, the maximum number of times cleaning should be performed exceeded that determined in the case of conventional specifications based on ITRS.
KEYWORDS: Photomasks, Error analysis, Lithography, Semiconducting wafers, Line edge roughness, Spatial frequencies, Matrices, Monte Carlo methods, Process engineering
With ever decreasing feature sizes, the control of mask CD errors is becoming increasingly critical in order to realize a good lithographic performance.
In our previous study, mask CD errors were classified on the basis of spatial frequency into the following three categories: local CD error, global CD error, and line edge roughness (LER). If the period of a mask CD error exceeds the optical proximity effect (OPE) range, the mask CD error is classified as a global CD error. If the period is almost equal to the OPE range, the mask CD error is classified as a local CD error. As compared with the OPE range, the LER has very small spatial frequency. Introducing the concept of mask enhancement factor (MEF) for local and global CD errors, we examined the ratio of local MEF to global MEF for 1-dimensional dense and isolated line patterns.
In this paper, we build on our previous study, dealing with 2-dimensional rectangular patterns. In addition, we introduce the “local MEF matrix,” which reflects the characteristics of a pattern layout and aids the estimation of local CD errors. Furthermore, we discuss the required mask specifications of 2D patterns for low-k1 lithography.
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