Dr. Yuyang Bian Profile

Dr. Yuyang Bian

at Shanghai Huali Integrated Circuit Corp.

SPIE Involvement:

Author

Publications (7)

SPIE Journal Paper | 4 November 2022

Process window improvement for fin cut layer in self-aligned double-patterning process based on backscattered electron imaging

Yu Zhang, David Wei Zhang, Yuyang Bian, Biqiu Liu, Cong Zhang, Jun Huang, Jiawang Song, Yang Gao, Qiang Zhou, Wei Chen, Siqun Xiao, Shmuel Ben Nissim, Kevin Houchens, Omri Baum, Amit Zakay, Tal Ayzik, Yaniv Abramovitz

JM3, Vol. 21, Issue 04, 041605, (November 2022) https://doi.org/10.1117/12.10.1117/1.JMM.21.4.041605

KEYWORDS: Etching, System on a chip, Image processing, Sensors, Lithography, Semiconducting wafers, Distance measurement, Process control, Transistors, Signal to noise ratio

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SPIE Journal Paper | 19 September 2022

Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement

Yu Zhang, David Wei Zhang, Yuyang Bian, Biqiu Liu, Cong Zhang, Jun Huang

JM3, Vol. 21, Issue 03, 034001, (September 2022) https://doi.org/10.1117/12.10.1117/1.JMM.21.3.034001

KEYWORDS: Polarization, Diffraction gratings, Diffraction, Scanning electron microscopy, Overlay metrology, Etching, Metrology, Optical testing, Lithography, Image processing

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Proceedings Article | 13 June 2022 Presentation

A holistic study of edge placement error on fin cut layer in self-aligned double patterning process

Yuyang Bian, Biqiu Liu, Xijun Guan, Xiaobo Guo, Cong Zhang, Wenzhan Zhou, Jun Huang, Yu Zhang, Jiawang Song, Yang Gao, Shmuel Nissim, Kevin Houchens, Omri Baum, Qiang Zhou, Zaisan Yang, Amit Zakay, Tal Ayzik, Yaniv Abramovitz

Proceedings Volume PC12053, PC120530D (2022) https://doi.org/10.1117/12.2614221

KEYWORDS: Overlay metrology, Double patterning technology, Edge roughness, Scanning electron microscopy, Manufacturing, Line width roughness, Line edge roughness, Integrated circuits, Electron microscopy, Critical dimension metrology

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Proceedings Article | 26 May 2022 Poster + Presentation + Paper

Advanced dose control using random logic device patterns and massive metrology in a foundry high-volume manufacturing environment

Wen Zhan Zhou, Kan Zhou, Yu Yang Bian, Yu Zhang, Ijen van Mil, Robbin Zhu, Jo Zhu, Ivan Mao, Kai yuan Chi, Xuechen Zhu, Kelvin Pao, Pei Wang, Lilla Wang, Abdalmohsen Elmalk, Gary Zhang

Proceedings Volume 12053, 120532A (2022) https://doi.org/10.1117/12.2638430

KEYWORDS: Metrology, Semiconducting wafers, Control systems, Optical proximity correction, Logic devices, Reticles, Stochastic processes, High volume manufacturing, Finite element methods, Error analysis

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One of the most critical challenges in the lithography process is to effectively control all critical patterns over the full exposure field, across wafer, and from lot to lot consistently. ASML’s advanced dose-control solutions have been widely adopted to control CDU of critical patterns. A new high-order dose-control capability is introduced with extended controllability over a larger number of patterns to mitigate the stochastic effect and optimize dies-in-spec performance. Traditionally, designed marks or patterns are placed in the die for dense metrology sampling required for the advanced high-order dose-control applications. However, this method has a few disadvantages especially for logic foundry use cases. For example, the designed marks are often not identical to random logic critical patterns, thus leading to a situation in which marks are controlled well while device patterns are not. In-die placement of the designed marks normally imposes constrains in device layout, which is not acceptable in some cases such as large-die layouts. A preferred approach would be to measure directly on device-critical and/or weak-point (WP) patterns. But this brings up another challenge in metrology of device WP patterns. With conventional CDSEM the amount of data points is limited by the tool throughput. WP patterns are typically 2D patterns, with normally a high noise contribution from local variations (due to resist stochastics) and metrology. Thus to suppress the local variations, averaging of many local measurements of 2D WP patterns is preferred. This requires a high throughput e-beam metrology tool capable of making massive amount of inline measurements within a given cycle time. To address these challenges, we have developed a method of using yield-limiting device patterns to directly control dose and thus improve CDU. Close to 100 WPs per in-die location have been selected with a dense die coverage to minimize the contribution to global CDU from the local variations and metrology noise. A high-speed e-beam metrology tool is used to measure all the selected WP patterns. A CDU budget breakdown (BB) has been analyzed to identify and quantify CDU contributors, such as reticle fingerprint, OPC error, local CDU, metrology noise, etc. Different in-die WP sampling and dose-control methods are studied in this work to achieve optimal CDU correction while keeping the metrology cycle time under control for HVM implementation.

Proceedings Article | 19 August 2021 Presentation + Paper

The importance of in-die sampling using E-beam solution on yield improvement

Yu Zhang, Biqiu Liu, Cong Zhang, Yuyang Bian, Song Gao, Yifei Zhu, Xiaobo Guo, Jun Huang, Yaniv Abramovitz, Qiang Zhou, Uri Smolyan, Omri Baum, Shmuel Ben Nissim, Alexander Vipolzov

Proceedings Volume 11611, 116111X (2021) https://doi.org/10.1117/12.2585391

KEYWORDS: Overlay metrology, Instrument modeling, Semiconducting wafers, Measurement devices, Wafer-level optics, Mathematical modeling, Yield improvement, Etching, Optical testing, Data modeling

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