KEYWORDS: Analog electronics, Design for manufacturing, Metals, Resistance, Capacitance, Databases, Back end of line, Tolerancing, Mirrors, Manufacturing
Electrical Design-for-Manufacturability (DFM) checks are developed to quantify layout enhancements and their impact on circuit performance for analog designs. A database containing circuit topologies of analog matched devices is built. Then, connectivity checks scan the schematics for topologies from the database. If a matching topology were detected, the matched devices are mapped to layout for layout matching checks. If layout mismatches are detected, electrical DFM checks are used to quantify the imbalance in terms of parasitic resistance and capacitance. The electrical DFM checks are applied to quantify the impact due to routing, fill, and DFM fixing on three, 22nm analog design blocks. Fill insertion’s contribution to RC change is the greatest followed by routing and DFM fixing, with a maximum change of 7%, 5%, and less than 1%, respectively. Symmetry-aware layout insertions preserve the matching of electrical parameters, showing zero mismatch. All designs pass electrical DFM checks as results are within the expected design tolerances.
A symmetry-aware DFM layout insertion flow for matched circuits is developed for enhancing analog and mixed-signal designs. Pattern capture is used to categorize the matched circuits to unique groups of layout patterns and store them in a pattern database, in which each pattern has an associated group identification, a match location, a region of extent, and a symmetry constraint. Using the stored information in the pattern database, DFM layout insertions are applied to the base pattern and replicated for the symmetric patterns to generate an optimized layout, thus preserving the original symmetry. The impact of the DFM insertions on analog circuit performance was quantified using electronic simulators. The application of symmetry-aware DFM enhancements to analog designs achieves nearly 100% DFM compliance with negligible 0.1-0.2% impact to analog electrical parameters.
In this paper, we propose methodologies used in a software system for checking process friendliness (including lithography friendliness) and routability (including pin accessibility) of standard cells. In the process of designing physical layouts of standard cells, it is essential to consider their process friendliness since specific cells have very high tendencies to create process weakpoints (which include lithography hotspots) after their instances are placed and routed. On the other hand, at advanced process nodes, the routability of standard cells must also be considered since there are combined trends of increasing pin densities and increasing design rule complexities. Experimental results show that our software system is able to effectively detect problematic standard cells which have critical process friendliness and/or routability issues.
KEYWORDS: Design for manufacturing, Analog electronics, Manufacturing, Chemical mechanical planarization, Design for manufacturability, Metals, Extremely high frequency, Yield improvement, Digital electronics, Transceivers
A suite of DFM enablement is enhanced to address the unique needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules and patterns are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies. Using DFM-aware fill, a 2% quality-factor loss for a mmWave inductor operating at 30 GHz is shown to be sufficient for meeting manufacturing planarity requirements.
Layout context plays a very significant role in printability of layout shapes, and hence it is extremely critical to include layout context information while performing printability checks. In this paper, we are proposing a unique approach of analyzing layout context geometries and use Machine Learning (ML) technique to predict lithography hotspots. Our method uses past lithography simulation results to evaluate geometry margins and profile them in simple geometry rules. The markers of these rules then analyzed by our unique context analyzer and generate data set for train Arterial Neural Network (ANN). Later this trained ANN model used for predictions on new input designs. In this paper, we will also present results to highlight how our approach is better in the accuracy of lithography hotspots detection in comparison to previous work related to pattern matching and machine-learning techniques.
At advanced and mainstream process nodes (e.g., 7nm, 14nm, 22nm, and 55nm process nodes), lithography hotspots can exist in layouts of integrated circuits even if the layouts pass design rule checking (DRC). Existence of lithography hotspots in a layout can cause manufacturability issues, which can result in yield losses of manufactured integrated circuits. In order to detect lithography hotspots existing in physical layouts, pattern matching (PM) algorithms and commercial PM tools have been developed. However, there are still needs to use DRC tools to perform PM operations. In this paper, we propose a PM synthesis methodology, which uses a continuous refinement technique, for the automatic synthesis of a given lithography hotspot pattern into a DRC deck, which consists of layer operation commands, so that an equivalent PM operation can be performed by executing the synthesized deck with the use of a DRC tool. Note that the proposed methodology can deal with not only exact patterns, but also range patterns. Also, lithography hotspot patterns containing multiple layers can be processed. Experimental results show that the proposed methodology can accurately and efficiently detect lithography hotspots in physical layouts.
The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit’s mismatch. To overcome the problem and improve the turn-around time, we proposed our smart “anchoring” placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.
KEYWORDS: Transistors, Metals, Databases, Resistors, Lithium, Digital electronics, Error analysis, Capacitors, Analog electronics, Manufacturing, System on a chip, Semiconductors, Silicon, New and emerging technologies
Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing
processes, and variations. This paper presents analog verification flow with five types of analogfocused
layout constraint checks to assist engineers in identifying any potential device mismatch and
layout drawing mistakes. Compared to several solutions, our approach only requires layout design,
which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation
and allows seamless integration into the layout environment with minimum disruption to the custom
layout flow. Our user-friendly analog verification flow provides the engineer with more confident with
their layouts quality.
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