With the vigorous development of data centers, optical fiber interconnection technologies have been evolved from multimode optical fiber (MMF) parallel transmission to CWDM4 single-fiber bidirectional (Bidi) transmission. What’s more, requirements for miniaturization of optical transceivers are put forward. This paper studies a CWDM4 Bidi transceiving module based on hybrid integration technology. Six optical interleavers in serial and parallel connection function as the CWDM4 wavelength division multiplexer and demultiplexer, while an optical circulator is designed with the three inputs/outputs at the same side, which helps to realize Bidi transmission. The former is based on integrated optics and the latter is based on micro-optics. Through the hybrid integration of integrated optics and micro-optics technologies, the transceiving module is minimized and can be integrated into a QSFP module.
This paper reports an optical tunable filter array (TFA) based on a LCOS (liquid crystal on silicon) chip. The input broadband optical beam is first dispersed by a bulk grating and then incident on the LCOS chip. The LCOS chip is phase-only modulated and constructed as a dynamic reflective phase grating. The phase modulation is adjusted to meet the Littrow angle for a specified passband wavelength and thus the optical beam corresponding to this wavelength is steered to the output. The input/output optical beams are coupled to optical fibers with a dual-fiber collimator. Four dualfiber collimators are vertically aligned as the inputs/outputs and the pixels of the LCOS chip are vertically allocated as four independent zones. Thus the device can act as a 4-channel TFA, which is assembled and functionally demonstrated.
A digital carrier synchronization module with high working frequency is indispensable for high-speed digital coherent optical receivers to recover the transmitted symbols. We proposed a method to increase the working frequency of the digital carrier synchronization (DCS) module based on the commonly used M’th power algorithms. Parallel architecture can increase the throughput of digital signal processing (DSP) modules for a given working frequency. pipelined architecture (PA) leads to a reduction in the critical path, and thus it can be exploited to increase the throughput of DSP modules by increasing the working frequency. It is demonstrated that in PA the working frequency is not limited by the computation time of the M’th power subfunction with the highest complexity because it is feedforward and thus pipelining registers can be introduced to reduce the critical path inside it. Instead, the phase unwrapping subfunction (PUS) becomes the bottleneck of the working frequency because it requires the immediately preceding result and cannot be implemented in PA, which results in the longest critical path among the DCS module. To solve this problem, we propose a feedforward look-up-table-based PUS design that can greatly reduce the critical path and increase the working frequency. Experimental DCS implementation in a Xilinx Virtex7 field programmable gate array shows that with this method the working frequency of the DCS module for quadrature phase-shift keying (QPSK) signals can be increased by 63.8%. Furthermore, using experimental and simulation data, it is demonstrated that the performance of the DCS module with increased working frequency is close to that of the off-line DCS algorithms for QPSK signals.
High-Definition Multimedia Interface(HDMI) can carry high quality multi-channel audio data and can carry all
standard and highdefinition video formats. To send the information form video source to the display unit, the HDMI
cable which carries four differential pairs is used. Now HDMI 1.3 increases its single-link bandwidth from 165MHz
(4.95 gigabits per second) to 340 MHz (10.2 Gbps) to support the demands of future high definition display devices, so
the traditional copper wire cable imposes limits on signal transmission distance and signal quality at so high speed.
Optical fiber is of low dispersion, which in turn has the strength of longer signal transmission distance and better signal
transmission quality in comparison to the traditional copper wire cable. So the optical extender consisting of two
modules - one transmitter and one receiver- is developed. The transmitter connects to a computer/DVD player etc. The
receiver connects to a display. Between the two modules, four-core ribbon fibre is used to transmit the video and audio
signals. HDMI needs four differential pairs, so we design the parallel optical transmitter based on VCSEL array and
VCSEL driver chip HXT3404 from Gigoptix and the parallel optical receiver based on PIN array and transimpedance
amplifier chip HXR3404. Each channel can reach 3.125Gbps, so the data speed of the optical extender is 12.5Gbps. The
experiment shows that the optical extender can transfer the video and audio data to the display uint 100 meter away.
The configuration of polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. An
additional optical layer with light waveguide structure is used in conventional PCB to construct EOPCB. Light
waveguide core layer mould is made with SU-8 photolithograph. Polymer light waveguide layer which is embedded
between multiplayer PCB is made in experiment by Doctor-blading technology for large size application. Vertical cavity
surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array is used as optical
receiver array. A MT-compatible direct coupling method is presented to couple light beam between optical
transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on the PCB can
transmit to another processor element chip on the same PCB board through light waveguide interconnection in EOPCB.
So optical interconnection between chip to chip for parallel multiprocessor system can be reailzed by EOPCB.
A three-dimensional (3-D) 4×4×4 optical interconnect Mesh network scheme for parallel multiprocessor system based
on polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. The Mesh
topological structures of light waveguide interconnects for processor element chip-to-chip on a board, and board-toboard
on backplane is constructed. The system consists of 64 processor element chips interconnected in a 3-D Mesh
network configuration. Every processor board comprises 4x4 processor element chips with Mesh interconnection.
Board-to-board Mesh interconnects are established on a backplane through light waveguide Mesh interconnect
topological structure. An additional optical layer with light waveguide structure is used in conventional PCB to construct
EOPCB. Vertical cavity surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array
is used as optical receiver array. A MT-compatible direct coupling method is presented to couple light beam between
optical transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on a board can
transmit to another processor element chip on another board through light waveguide interconnection in the backplane.
So 3-D optical interconnection Mesh network for parallel multiprocessor system can be reailzed by EOPCB.
KEYWORDS: Switches, Satellites, Switching, Broadband telecommunications, Data modeling, Network architectures, Very large scale integration, Process modeling, Laser applications, Internet
Buffered crossbar switches are now becoming very attractive for the high performance packet switches. An architecture that combines the VOQ architecture and internal buffers can eradicate the HOL problems and reducing the output contention. The architecture predominance and the internal distributed arbitration can fit the broadband satellite networks very well. We propose a new scheduling scheme named Rate Durative (RD), which a VOQ is served continuously at the same time considering its priority level under certain rules. Our scheme was shown to handle traffic more efficiently and better than previous schemes. In addition, this scheduling scheme also supports QoS very well
Currently the mainstream technology of SAN is SAN storage virtualization and its implementation. The switch-based storage virtualization embeds the virtualizer in the core of the storage networking fabric in an "intelligent switch" rather than an appliance or a host. This paper describes the SV-FC SAN switch's hardware and software architecture. The main aid of design and implementation the switch is to give a new way to realize FC-SAN storage virtualization. Storage virtualization modules are embedded in the switches firmware. The switch can provide simple and friendly interfaces for users to configure and manage the FC SAN.
This paper focuses on the problem of designing a large 256×256 high-performance broadband packet (or ATM) switch. Early packet switch research concentrated on using N×log2N structures with buffers at each switch element. As a result, the nude number and the cost of such kinds of switches become prodigious and consequently could not have more practical significance. In this paper, we provide a method to design a kind of architecture containing fewer nodes. The distribution network of this new architecture based on the knockout theory has very low internal blocking, similar to that found in large 256×256 single crossbar networks, but the complexity and cost are less than that of single crossbar networks. A Balanced Incomplete Block Design (BIBD) in Combinatorics is provided to help construct the architecture. With this method, the mapping function between the input ports and the crossbars can be realized by a serial of mutually orthogonal Latin Squares (MOLS). Moreover, statistical tools are used to calculate the possibility of internal blocking of the network and to make a comparison between the improved architecture and the common one.
In the parallel processing system, large numbers of processors are interconnected in order to improve the performance of the computer, such as the symmetric multiprocessor (SMP) architecture. When the basic node is an SMP or a computer having a single processor, the characteristics of an interconnection networks are important factors which influence the performance of the entire system. Fibre Channel (FC) has a lot advantages, such as excellent scalability; the bandwidth is large; delay time is short and fault tolerance is large. It is assumed that an SMP is used for a basic node. We construct the cluster system using FC as interconnection network, which are a fabric method and a FC Arbitrated Loop (FC-AL) method. According the method, if the number of nodes supported by the interconnection network is small, the addition of extra nodes can be added at small expense. The bandwidth of each node is large, the delay time is short, and the fault tolerance effect is large in the interconnection network. In the case of connecting to a shared disk, a large bandwidth is provided and time required for gaining access to the shared disk becomes short.
A chip-to-chip optical interconnection solution on PCB is presented in this paper. Both electrical and optical interconnections are used in common printed circuit board (PCB) to construct electro/optical PCB (EOPCB). An additional optical layer with waveguide structure is used in the PCB. So the EOPCB integrates the information medium "light" into the board. Optical transmitter is vertical cavity surface emitting laser (VCSEL) array. Optical receiver is PIN array. VCSEL array with its driver IC chip and PIN with its receiver IC chip are bonded with LSI chip by ball-grid array (BGA) technology. Then the LSI chips with VCSEL and PIN arrays are bonded on PCB by surface-mount technology (SMT). Multimode waveguides are used as optical layer in PCB. In order to couple light beam between optical transmitter/receiver with waveguide layer, a direct coupling method by the waveguide with 45° end face is presented. VCSEL chip is placed close to the 45° end face of the waveguide. The light beams from VCSEL array are emitted into the 45° end face directly and reflected by 90°, then coupled into the waveguide layer. No microlens arrays are needed for collimating light beam array in this configuration. A proof-of-principle experiment is made to verify the feasibility of this approach.
This paper describes the design of an OIF-approved 10Gbps very short reach parallel optical interconnect demonstrated system. It is a 12x1.25Gb/s channel parallel optics solution, leveraging the low cost transceiver (850nm VCSEL), and CMOS (SERDES) technologies originally developed for Gigabit Ethernet. The demonstrator comprises of SONET/SDH serial OC-192 interface, CPLD based convert IC, 1.25Gbps 12-channel parallel optical transmitter and receiver. The transmitter includes a 12-channel array of 850nm VCSEL, a 12-channel VCSEL driver LSI, and a precise coupling structure for 12 multi-mode-fibers ribbon. The receiver consists of a 12-channel array of pin-PDs, a 12-channel receiver LSI, and a precise coupling structure for 12 multi-mode-fibers ribbon. A CPLD chip, which maps the OC-192 framer onto the parallel optical links, and reassembles it after detection, has been developed. We also present the coupling package configuration for VCSEL arrays to fiber ribbon.
This paper reported an improved optical switching network configuration based on optical interconnection technology with vertical cavity surface emitting laser (VCSEL) array. The optical switching network consists of two-level optical interconnection backplane. It can connect 64 nodes with parallel optical links. The first level of optical interconnection backplane includes eight 8×8 crossbar interconnect sub-networks. Instead of one 8×8 crossbar interconnect sub-network in the second level of the optical interconnection backplane adopted in our original configuration, the second level of optical interconnection backplane has two 8×8 Crossbar interconnect sub-networks in this improved configuration. So the blocking rate is decreased. VCSEL-based parallel optoelectronic I/O interface is used as O/E conversion. Every I/O parallel interface between optical interconnection network and every node includes 18 VCSEL emitter pixels, 18 PIN receiver pixels. In order to couple 18 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A configuration of coupling packaging for the VCSEL pixel array to the fiber array with 45° end surface is also presented in this paper. An optical data transmission rate between interconnection nodes is 5Gb/s which is transmitted by the optical fiber ribbon-based parallel optical data links with 2 channels at data rate of 2.5Gb/s per channel. The aggregate bandwidth of 360Gbps for an 8×8 Crossbar optical fiber interconnect network backplane is achieved. The reliability of the fiber array with 45° end surface is tested in our experiment.
A novel hybrid electrical optical Clos switch network for multiprocessor cluster system was presented. For multiprocessor cluster system of 128 hosts, the novel optical Clos network includes 16 basic modules, a passive optical fiber backplane with (8×15)×16 which has a total of 1920 optical data channels and a signaling control system. The basic module is composed of the input line cards of 8 hosts, a single chip of 16×16 crossbar switch, parallel transmitting VCSEL modules for fan-out of (16-1)optical fiber channels and (16-1)×1 optical combiners. The passive optical fiber backplane of very large capacity and high density, based on linear VCSEL arrays and fiber ribbon technology, is to be used to interconnect between hosts of different sub-clusters. The routing of the optical Clos switch network is decided by a signaling control system. Compared with high performance electronic system, this technology offers a relatively easy and simple means of communicating large amount of information between hosts, and lower delay time.
A novel photonic switching network with vertical cavity surface emitting laser (VCSEL) array packaging for parallel multiprocessor cluster system is described. The parallel multiprocessor cluster system provides 64 serve nodes connected by photonic switching network with parallel optical links. There are eight cluster subsystems in the system. Each subsystem includes eight computing nodes and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O parallel interface. Every I/O parallel interface between optical interconnection network and every computing node includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. In order to couple 16 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A packaging structure for optical fiber array interface is presented. As the position slots of optical fiber array interface are formed by VLSI photolithography and IcP etch techniques, and etching depth is smaller compared with V-groove slot, the high precision slots with 25Ojtm pitch can be obtained. A configuration of coupling packaging for 16 VCSEL pixel array to 16 fiber array with 45° end surface is also presented in this paper.
A photonic switching network for parallel multiprocessor cluster system using vertical cavity surface emitting laser (VCSEL) arrays is described. The parallel multiprocessor cluster system provides 64 server nodes interconnected by optical interconnection network with parallel optical links. There are 8 cluster subsystems in the system. Each subsystem includes 8 computers and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O interface. An optical data transmission rate between computers is 5Gb/s which is transmifted by the optical fiber ribbon-based parallel optical data links with 2 channels at data rate of 2.5Gb/s per channel. Every I/O interface between optical interconnection network with each computer includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. VCSEL emitter pixels transformed electrical signals from PCI bus of computer into optical signals, where PIN receiver pixels transformed optical signals from optical interconnect network backplane into electrical signals. The whole optical interconnection network is composed of two level optical interconnect backplanes. A total of 64 computers propagating for data communication of 8 subsystems would be realized.
An optical interconnection network with parallel optical links for multiprocessor cluster system of 256 nodes is described. There are 16 subsystems in the system, in which each subsystem includes 16 computers and an optical fiver-ribbon interconnection plate of 16X16 crossbar interconnection network with VCSEL-based opto-electronic
interface. An optical data rate between computers is 5Gb/s which is transmitted by the optical fiber-ribbon based parallel optical data links with 4 channels at data rates of 1.25Gb/s per channel. Every interface between optical interconnection network and each computer includes 16X4 VCSEL pixels, 16X4 PIN pixels and (1X16)X4 electrical
switch. The whole optical interconnection network is composed of two level optical networks. There are sixteen optical fiber-ribbon interconnection plates of 16X16 crossbar interconnection network in the bottom level. The top level optical interconnection network would be an optical fiber-ribbon interconnection plate with a total of
2084 data channels propagating for communication of 16 subsystems.
This paper presents a novel multibuffer-shared ATM switching architecture based on optical interconnects and optoelectronic hybrid crossbar modules. The core of this switching architecture is the 16 X 16 CMOS-SEED crossbar switching module, and the optical interconnects between the input interface and switching core provide high-speed data paths. Many buffers placed in an output module of the interface are partial shared, which take advantages of output buffer and shared buffer, so these buffers are used more effectively than the output buffer. And these shared buffers bring an advantage that the speed of the accessing each of these buffers is not need very high due to these buffers can write/read many cells in a parallel way. The performance of this ATM switching system is analyzed under the uniform traffic and bursty traffic. The simulation results show that the cell loss probability of this ATM switching system is less than 10e-9 under the uniform traffic with 12-cell length of each shared- buffer, and the cell loss probability is less than 10e-9 under the bursty traffic with 160-cell length of each shared-buffer.
IP traffic on the Internet and enterprise networks has been growing exponentially in the last several years, and much attention is being focused on the use of IP multicast for real-time multimedia applications. The current soft and general-purpose CPU-based routers face great stress since they have great latency and low forwarding speeds. Based on the ASICs, layer 2 switching provides high-speed packet forwarding. Integrating high-speed of Layer 2 switching with the flexibility of Layer 3 routing, Layer 3 switching (IP switching) has been put forward in order to avoid the performance bottleneck associated with Layer 3 forwarding. In this paper, we present a prototype system of a scalable IP switching based on scalable ATM switching fabric and optical interconnect. The IP switching system mainly consists of the input/output interface unit, scalable ATM switching fabric and IP control component. Optical interconnects between the input fan-out stage and the interconnect stage, also the interconnect stage and the output concentration stage provide high-speed data paths. And the interconnect stage is composed of 16 X 16 CMOS-SEED ATM switching modules. With 64 ports of OC-12 interface, the maximum throughput of the prototype system is about 20 million packets per second (MPPS) for 256 bytes average packet length, and the packet loss ratio is less than 10e-9. Benefiting from the scalable architecture and the optical interconnect, this IP switching system can easily scale to very large network size.
KEYWORDS: Switching, Asynchronous transfer mode, Optical interconnects, Solar concentrators, Interfaces, Computer simulations, Optoelectronics, Electronic components, Signal processing, Free space optics
A growable multistage ATM switching architecture based on optical interconnect is presented in this paper. The interconnect stage, core of the 3 stages architecture, is composed of 16 by 16 CMOS-SEED optoelectronical hybrid ATM switching modules. Since the interconnect stage is memory- less, electronic buffers are provided in the output concentrator stage, and the buffers are partial shared to be used effectively. Optical interconnects between the pair- input expansion stage and the interconnect stage, also the interconnect stage and the output concentrator stage provide high-speed data paths, for example 622Mb/s or 2.4 Gb/s. Both the with lower speed control signal and the complicated logical processing are carried out in the electronic devices. With 64 ports of OC-12 interface, the maximum throughput of the prototype system is about 40 gigabits per second, an the packet loss ratio of this ATM switching system is less than 10e-9. Taking advantages of high speed of the optical interconnect and the high density, flexible logical processing of the electronic devices, the ATM switching of the optical interconnect and the high density, flexible logical processing of the electronic devices, the ATM switching system has favorable potential to scale easily to very large network size, for example 256 ports of OC-48 interface.
In this paper, we first demonstrate that the signal received from the laser underwater target detection system may be chaotic through phase space reconstruction, correlation dimension analysis and Lyapunov exponent calculation. Then the result of the correlation dimension analysis is used to construct a neural network predictor which is considered as an approximation of the basic dynamics of the received signal. Finally we introduce a chaos-based detection method and apply it to detect the underwater target. The performance of this new method is superior to that of the conventional method.
The information format in the experimental underwater laser system is discussed. Two-pulse modulation for the laser is proposed. This method clearly reduces the modulated laser pulse's vibration range which is caused by the random change of Q switch's trigger of the laser. Thus the reliability of the communication is increased. The hardware and software flow chart of the modulator are shown in this paper.
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