2.1

Slit geometry

One of the great advantages of this silicon process is that the lateral shape of the apertures can be manufactured with almost arbitrary shape and ultimate precision. The mean single slit width (24 μm nominal) could be reproduced with <0.5 μm deviation. This value can be further improved by down-selection (eight slit chips are produces on one wafer in parallel). Slit width variation along the slit is below 0.4 μm peak-to-valley. A main source of uncertainty for slit width is measurement uncertainty. Compared to other technologies such as machining or electro-forming, these values are excellent and facilitate the design of new applications.

Accordingly, slit length (24 mm by design) can be realized with deviations of <5 μm. The accuracy of this parameter was not optimized since it is not performance critical. The center lines of the individual slits were nominally separated by 480 μm, measurement yielded deviations of less than ±0.2μm (corresponding to a slit-to-slit parallelism of better than 4 arcsec). It is evident that lateral feature precision is one of the major advantages of this technology, since it makes use of well elaborated lithographic processes.

2.2

Planarity

Slit planarity is a major issue especially for longer slits, since the slit plane is required to remain in focus of the optical system all over the slit length. Fast optical systems (like EnMAP with f/# = 3) have a depth of focus of ~10 μm, meaning that slit planarity is often required to be better than ±5 μm. This is a critical value for most metallic solutions since inherent material stress tends to bend the free-standing structures of slits with high aspect ratio.

Figure 2-1 shows the surface form measurement of a structured silicon chip. The chip is ~30 mm long and the two 24 mm long slits can be seen as a white line in the center of the false-color plot (the two longer, neighboring white lines are different structures of no further interest). As can be seen, the planarity all over the slit chip is excellent. The peak-to-valley bending, i.e. deviation from a perfectly flat plane, of the whole chip is less than 3 μm, in the vicinity of the slit apertures, and this is the performance relevant area, it amounts to less than 2 μm only.

Figure 2-1:

False-color plot of the slit chip surface. Planarity is better than 3 μm peak-to-valley over the whole chip diagonal. Planarity of the 24 mm long slit apertures (white line at the center) is better than 2 μm peak-to-valley. As expected, the chip is bent almost spherically due to residual layer-stress. Image by Fraunhofer IMM.

The form of the bent chip is in good approximation spherical. The reason for this is residual stress difference between the silicon and insulating layers of the wafer. This effect has been counter-acted by stress compensation layers.

It is important to note that not only the regions on both sides of the double slit are flat, but also the thin, slit separating bar does not protrude out of the common plane. A closer view on a single slit’s membranes on both sides of the respective aperture shows that they are levelled within less than 200 nm, i.e. there is no offset between the local slit planes on either sides of the aperture.

2.3

Slit thickness and vertical structuring

For the process applied for EnMAP double slit device, a so called SOI (Silicon-On-Insulator) wafer with diameter of 125 mm has been used. It consists of three layers (see Figure 2-2): The device layer is bonded via a 1 μm thick SiO2-layer onto the much thicker and load-bearing handle layer, which in our case is 0.5 mm thick. Both device and handle layers are of pure crystalline silicon.

Figure 2-2:

Vertical structure of an SOI wafer used for double slit manufacturing (see text). The top and bottom layers (gray) are of pure, crystalline silicon, while the intermediate box-layer consists of SiO₂. Image by Fraunhofer IMM.

In a process involving several lithography and etching steps (Fraunhofer IMM), all three layers are structured such that the two slit apertures are formed. the slit thickness is mainly defined by the thickness of the device layer. SOI wafers can be procured off-the-shelf with device layers with few to tens of micrometers thickness. In addition, the device layer can be etched to the proper thickness, if necessary. The thickness of the device layer varies by less than ±0.5 μm from wafer to wafer. However, thickness uniformity of one slit chip is far better (smaller than ~0.1 μm), as this parameter is well-controlled by the wafer manufacturing process.

The vertical structure of the two slits, which can be seen in Figure 2-3, is driven by the specific requirements of the EnMAP slit assembly. Since light impinges from the structured side of the slit (i.e. from below in Figure 2-3), slanted surfaces had to be avoided in order to minimize stray light. The orthogonal walls help greatly to reduce unwanted scattering. For other systems allowing light to impinge from the “flat” side of the slit chip, the walls might be chosen to have a certain angle with respect to the optical axis. Detailed stray light simulation was performed to find an optimum.

Figure 2-3:

SEM images of double slit cross-section (left hand side) and a single slit with larger magnification (right hand side, rotated by 180°). Direction of light propagation is downwards (left) and upwards (right), respectively. Images by Fraunhofer IMM.

As can be seen in Figure 2-3, the slit edges of the membrane can be produced extremely sharp. Edge radii below 1 μm can be realized. This helps avoiding scattered light from the slit edges, which is often one of the main stray light sources and deteriorates signal-to-noise ratio of the instrument.

2.4

Optical density and reflectivity

Both sides of the slit chip were coated with a high-reflective layer to prevent damage by high radiant power absorption during a failure mode of the instrument (see section 4.4). The applied broadband reflective layer of 150 nm Aluminum-Neodynium (AlNd) was sputtered onto all surfaces of the single chips. Special attention was paid to the coverage of all slit surfaces, even the micro-structured regions close to the apertures. The AlNd layer ensured light tightness of the slit structures, since uncoated silicon is transparent for wavelengths longer than ~1 μm. An optical density of better than OD7 was achieved, i.e. the residual transmittance was less than 10^-7.

For other scenarios, black coatings might be advantageous in terms of stray light suppression. As we show below for the micro-structured baffle, broadband, high absorbing coatings can be applied to the silicon parts. In this case, an additional thin metal layer could be necessary to ensure light tightness.

3.1

Field splitting mirror

The mirror has to be small and positioned close to the slit (focal) plane, because the inter-slit distance is only 0.48 mm and the diverging beams (~10° half angle corresponding to f/# = 3) would intersect after only ~1.3 mm behind the slit plane.

The mirror has been realized as a flat silicon chip glued to the slit chip, whereas one of the side surfaces of the mirror chip has been cut and polished to an angle of exactly 54.5°, and coated with gold (see Figure 3-1). The mirror chip is 0.87 mm thick and the mirror clear aperture is not larger than ~25 mm x 1 mm.

Figure 3-1:

Schematic of the integral silicon assembly showing slit chip, deflecting mirror and micro-structured baffle. The double slit aperture is indicated by a line, light is impinging from above. All three parts are positioned and bonded in a precise integration procedure by Fraunhofer IMM.

The mirror has been positioned and glued onto the slit chip with a precision of ~10 μm and deflects light passing through the SWIR channel slit but does not affect light passing through the other slit. Its final surface roughness is below 0.5 nm and the surface form error amounts to 16 nm peak-to-valley.

3.2

Micro-structured baffle

In order to suppress stray light, there has been included a micro-structured baffle on the opposite side of the slits. It also consists of a silicon chip, 0.42 mm thick, which is glued to the slit chip, whereas its backside surface provides a saw-toothlike structure thus very efficiently suppressing first order ghosts and stray light paths (Figure 3-2). The baffle structures are coated with a high absorbing, diffuse coating (“Acktar Fractal Black™”). The silicon structuring process of all parts was performed by Fraunhofer IMM.

Figure 3-2:

All-silicon baffle (before coating). Surface is saw-tooth structured and coated black in order to absorb stray light. The period of the structure is ~0.3 mm, the depth of the groves ~0.2 mm. Image by Fraunhofer IMM.

3.3

Thermal design and mounting

The thermal expansion behavior of silicon is very different from aluminum (which is the material of the optical bench). Its coefficient of thermal expansion (CTE) is almost 9 times smaller at room temperature. During thermal cycling, a direct transition Si-Al would lead to stress induced fracture of the brittle silicon structures. Therefore, the silicon parts (slit chip, mirror and baffle) were glued into a frame made from Invar (see Figure 3-3).

Figure 3-3:

Invar frame with mounted slit chip. The dark area on the slit chip is the micro-structured baffle. The slit chip is glued at four edges/glue pads to the frame. The frame itself is mounted to an aluminum structure via isostatic flexures. Image by Fraunhofer IMM.

The CTE of Invar is much closer to that of silicon (difference ~1x10^-6/K). Nevertheless, flexures in the Invar frame were introduced in order to absorb differential expansions. Similarly, flexures at the Al-structure provide isostatic mounting of the Invar frame.

4.1

Vibrational loads

Sine loads and random vibration loads (up to 2 kHz and 8 g root-mean-square) have been applied. Since the first Eigen-frequency of the assembly is close to 2 kHz, vibrational excitation of the assembly is not a big issue. The Eigen-frequencies of the more critical silicon parts – especially that of the bar between the slits – are 2.1 kHz and higher, so they are not significantly excited during random testing. This is highly advantageous since the silicon bar is brittle compared to a metal structure, for instance. In addition, a clash of the slit membranes only 24 μm apart, caused by excitation of a lateral mode of motion, would most probably destroy the thin structures immediately.

4.2

Shock loads

Shock loads can be much more severe for the silicon parts than random vibration excitation. Due to the brittleness of the material, small imperfections or bad design at critical positions can lead to elevated material stress levels and – ultimately – to fracture. Therefore, special attention was paid to both low-stress design, sufficient margins of safety and flawless manufacturing processes.

In addition, shock events are – in contrast to well predictable vibrations – able to excite the high-frequency modes of the tiny slit structures (membrane, slit bar). These parts can potentially answer with high-amplitude oscillations, which again can lead to stress-induced material failure or even collisions of close-standing double slit structure components (oscillating slit bar).

The assembly was successfully subjected to two different shock tests, according to mission requirements. The high-frequency plateaus of the qualification Shock Response Spectra (SRS) of the respective tests was 250 g (in between 1 kHz and 5 kHz) and 1350 g (6.5 kHz to 10 kHz), respectively. The SRS were calculated with a quality factor of Q=25.

4.3

Thermal loads

A standard thermal vacuum cycling test with qualification temperatures from -30 °C to +70 °C has shown the resistance of the assembly against temperature variations. The most critical aspects with respect to high thermal amplitudes are adhesive stress and stress induced by CTE mismatch. The latter can lead to deformation, fracture or slippage at interfaces between parts of different materials. As detailed above (section 3), several design measures have been taken in order to mitigate these problems from an early phase on.

4.4

Sun intrusion

In addition to the tests described above, a special sun intrusion test has been performed. This test simulates the scenario that the instrument – as a result of satellite control failure – directly looks into the sun. In this case, compared to nominal earth observation, a considerably increased radiative power enters the instrument and is directly focused onto the slit. Almost 30 W radiative power, focused down to a spot of 5 mm diameter imply an irradiance of more than 1.5 MW/m², which has to be withstood by the double slit device. For that reason, the whole slit chip has been coated with a broadband reflective layer reducing total absorbance to about 10%.

The test has been performed at the Solar Simulator of the DLR institute of solar research (Cologne). There, high energy Xenon lamps simulate the intense radiation of the sun with representative energy spectrum. The assembly passed the test by surviving irradiation for more than 15 seconds without permanent deformation or damage.