Zigzag nanosheets transistor introduction: a path for nanosheet FET architecture scalability

B. Vincent; J. Ervin

doi:10.1117/12.2613999

26 May 2022 Zigzag nanosheets transistor introduction: a path for nanosheet FET architecture scalability

B. Vincent, J. Ervin

Proceedings Volume 12052, DTCO and Computational Patterning; 1205204 (2022) https://doi.org/10.1117/12.2613999
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States

Abstract

This paper presents a new transistor design that enables scalability of a nanosheet field effect transistor (FET) architecture. By introducing an innovative patterning design for the nanosheets (a zigzag shape), the contacted poly pitch (CPP) can be reduced to a 30nm size. Semiconductor virtual fabrication was used to create virtual prototypes of this new device architecture and evaluate different process and design assumptions.

Conference Presentation

Citation Download Citation

B. Vincent and J. Ervin "Zigzag nanosheets transistor introduction: a path for nanosheet FET architecture scalability", Proc. SPIE 12052, DTCO and Computational Patterning, 1205204 (26 May 2022); https://doi.org/10.1117/12.2613999

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