Design and test of signal processing hardware for two-dimensional phased array digital multi-beam system

Teng Wang; Renhong Xie; Dengbo Sun; Jingwei Hu; Peng Li; Yibin Rui

doi:10.1117/12.2631423

1 May 2022 Design and test of signal processing hardware for two-dimensional phased array digital multi-beam system

Teng Wang, Renhong Xie, Dengbo Sun, Jingwei Hu, Peng Li, Yibin Rui

Proceedings Volume 12171, Thirteenth International Conference on Signal Processing Systems (ICSPS 2021); 1217107 (2022) https://doi.org/10.1117/12.2631423
Event: Thirteenth International Conference on Signal Processing Systems (ICSPS 2021), 2021, Shanghai, China

Abstract

With the increasing use of digital array radars, radar signal processing systems have higher performance requirements. This article introduces a signal processing hardware design for the two-dimensional phased array digital multi-beam system. Because of its digital multi-beam characteristics, it is very demanding on the radar signal processing system's computing power, processing speed, and data throughput. This paper proposes a design of signal processing hardware based on Xilinx FPGA Virtex-7 and two multi-core digital signal processors (DSP) to meet the requirements of two-dimensional phased array digital multi-beam system. Subsequent experiments and engineering practices show that this design scheme can fully meet the requirements of the system.

Citation Download Citation

Teng Wang, Renhong Xie, Dengbo Sun, Jingwei Hu, Peng Li, and Yibin Rui "Design and test of signal processing hardware for two-dimensional phased array digital multi-beam system", Proc. SPIE 12171, Thirteenth International Conference on Signal Processing Systems (ICSPS 2021), 1217107 (1 May 2022); https://doi.org/10.1117/12.2631423

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