Poster + Paper
15 March 2023 Investigation of plasma etching for interlayer dielectric planarization in high-efficiency deep-ultraviolet nanowire LEDs
Author Affiliations +
Conference Poster
Abstract
Nanowire array LEDs rely on an interlayer spacer dielectric to enable connection of many nanowires in parallel. Conventional solutions use spin-coatable materials such as polydimethylsiloxane (PDMS) or spin-on-glass (SOG), which are thermally and mechanically unstable. Alternatively, more stable dielectric materials such as SiO2 or Si3N4 can be used, however these materials deposit conformally, leading to significant surface topology above the nanowires prior to the etch back step. In this work, we present a method for removing this surface topology by utilizing a self-planarizing photoresist layer and a plasma etch which removes photoresist and SiO2 at the same rate. By performing this planarization process several times, surface features of height h > 1 μm can be reduced to less than 50 nm, allowing further etching of the SiO2 to expose the tips the nanowires and allow for reliable p-contact formation. Unlike CMP, this process only involves dielectric deposition and dry etching, and places no limitations on sample size and shape, making it ideal for research settings.
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bryan Melanson, Matthew Seitz, and Jing Zhang "Investigation of plasma etching for interlayer dielectric planarization in high-efficiency deep-ultraviolet nanowire LEDs", Proc. SPIE 12433, Advanced Fabrication Technologies for Micro/Nano Optics and Photonics XVI, 124330H (15 March 2023); https://doi.org/10.1117/12.2649333
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KEYWORDS
Etching

Photoresist materials

Dielectrics

Dry etching

Light emitting diodes

Nanowires

Plasma etching

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