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The pattern size of semiconductor circuits has been shrinking as technical advances continued. Defect control becomes tighter due to a decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained considerably shrunk circuit and ultra-high density pattern of sub – 20 nm tech devices. In this paper, we introduce two different types of process defects: one of the defects think related to mask blank surface status and the other defect may relate to etching chamber inner surface condition. By the experiment results, we will bring forward the possible defect generation mechanism. Based on this understanding, an appropriate solution by surface treatment methods to mitigate defects will be proposed.
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Yuan Hsu, Edison Yang, Mochihiro Shimizu, "Surface treatment to reduce process defects," Proc. SPIE 12494, Optical and EUV Nanolithography XXXVI, 124941A (28 April 2023); https://doi.org/10.1117/12.2646601