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As the semiconductor manufacturing technology node scales down in the deep submicron domain, hotspot detection becomes more challenging and geo-contextually dependent than ever before. The need to profile IC layout patterns based on geometrical commonalities becomes a significant demand either during IC layout design or manufacturing phases. Identified hotspots during the manufacturing phase are usually correlated to specific geometrical configurations sensitive to the lithography process or other manufacturing processes. Accordingly, identifying similar geometrical configurations is an important step toward locating potential hotspots. Once these hotspots are identified, their patterns can be provided to the router to avoid using these patterns and find other valid alternatives. Furthermore, in the IC design sign-off phase or Design Rules Check (DRC), layout profiling can identify patterns with high commonalities to these problematic patterns that potentially lead to a yield loss. In this paper, we introduce automated IC layout patterns topological profiling approach using Directional Geometrical Kernels (DGKs) to capture the context of patterns around a Point-Of-Interest (POI) in an IC layout, such as a hotspot. The DGKs pattern representation provides a direct one-to-one mapping with physical geometrical measurements centered by the POI and doesn’t need further feature extraction models or maps used by other pixelized gridded imagebased or density-based representations, which are both time and computational resources-consuming. The DGKs are decomposed into topological and dimensional components. This makes the mechanism of patterns topological profiling not in need of complex models and can be precisely fine controlled to produce adequate patterns profiling granularity that is not easily approached by other patterns profiling alternatives.
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