Formal verification in chip verification and study on its application practice

Qi Shao; Jiang Yan

doi:10.1117/12.2678898

8 May 2023 Formal verification in chip verification and study on its application practice

Qi Shao, Jiang Yan

Proceedings Volume 12635, Second International Conference on Algorithms, Microchips, and Network Applications (AMNA 2023); 126350N (2023) https://doi.org/10.1117/12.2678898
Event: International Conference on Algorithms, Microchips, and Network Applications 2023, 2023, Zhengzhou, China

Abstract

With the development of integrated circuit industry, the complexity of integrated circuit chip design is becoming higher and higher, and the difficulty of verification is increasing exponentially. Verifying that the RTL description is as expected has become an increasingly important part of the modern integrated circuit industry. Compared with the traditional dynamic simulation verification, formal verification belongs to static verification, and it does not need manual inputting excitation, and can achieve the advantages of 100% coverage. This paper mainly introduces the status of formal verification, what formal verification is, the prospect of formal verification in the future, and provides a formal verification tool (VC Formal DPV) application practice model and several practical methods to significantly optimize its performance by taking the divider as an example.

Citation Download Citation

Qi Shao and Jiang Yan "Formal verification in chip verification and study on its application practice", Proc. SPIE 12635, Second International Conference on Algorithms, Microchips, and Network Applications (AMNA 2023), 126350N (8 May 2023); https://doi.org/10.1117/12.2678898

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