FPGA-based pseudo-random ranks cyclic shift interleaving and de-interleaving design and implementation

Zhijin Wei; Yuan Wang

doi:10.1117/12.3004811

16 August 2023 FPGA-based pseudo-random ranks cyclic shift interleaving and de-interleaving design and implementation

Zhijin Wei, Yuan Wang

Proceedings Volume 12787, Sixth International Conference on Advanced Electronic Materials, Computers, and Software Engineering (AEMCSE 2023); 127871V (2023) https://doi.org/10.1117/12.3004811
Event: 6th International Conference on Advanced Electronic Materials, Computers and Software Engineering (AEMCSE 2023), 2023, Shenyang, China

Abstract

In modern communication systems, channel coding can be affected by noise and burst errors, reducing the error correction capability of the received decoding, and this problem is generally solved by interleaving [8]. In this paper, based on the requirements of a topic, an algorithm based on pseudo-random rank-and-file cyclic shift interleaving and deinterleaving that can satisfy multiple rates is proposed based on the commonly used packet interleaving and cyclic shift interleaving, and the algorithm is implemented on FPGA (Field Programmable Gate Array), and the correctness of the design and implementation is proved by comparing the results with MATLAB calculations

(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Zhijin Wei and Yuan Wang "FPGA-based pseudo-random ranks cyclic shift interleaving and de-interleaving design and implementation", Proc. SPIE 12787, Sixth International Conference on Advanced Electronic Materials, Computers, and Software Engineering (AEMCSE 2023), 127871V (16 August 2023); https://doi.org/10.1117/12.3004811

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