FPGA architecture for convolutional neural network training

Jianlang Chen; Danfeng Qiu; Yudong Xie; Liangzhou Huo; Xin Chen

doi:10.1117/12.3006102

10 October 2023 FPGA architecture for convolutional neural network training

Jianlang Chen, Danfeng Qiu, Yudong Xie, Liangzhou Huo, Xin Chen

Proceedings Volume 12799, Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023); 127993W (2023) https://doi.org/10.1117/12.3006102
Event: 3rd International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023), 2023, Kuala Lumpur, Malaysia

Abstract

Convolutional neural networks (CNNs) have been gradually applied to aerospace equipment in recent years. However, CNN requires a significant amount of hardware resources, while parameters need to be updated for different tasks in space. We propose an FPGA architecture for CNN training through a multi-module collaborative design strategy. On the basis of the intra-layer parallelism, we analyze the data storage and the operations to deduce forward and backward propagation on embedded devices. Based on the experimental results, the working frequency can reach 250 MHz and the performance is 15.9 GOPS. The resource usage and efficiency of this design are superior to those of other similar hardware acceleration platforms.

(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Jianlang Chen, Danfeng Qiu, Yudong Xie, Liangzhou Huo, and Xin Chen "FPGA architecture for convolutional neural network training", Proc. SPIE 12799, Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023), 127993W (10 October 2023); https://doi.org/10.1117/12.3006102

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