A transistor sizing method for standard-cell optimization considering lithography effects

Jia-Syun Cai; Pin-Yuan Su; Chien-Lin Lee; Kuen-Yu Tsai

doi:10.1117/12.3012028

10 April 2024 A transistor sizing method for standard-cell optimization considering lithography effects

Jia-Syun Cai, Pin-Yuan Su, Chien-Lin Lee, Kuen-Yu Tsai

Proceedings Volume 12954, DTCO and Computational Patterning III; 129540C (2024) https://doi.org/10.1117/12.3012028
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.

Conference Presentation

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Jia-Syun Cai, Pin-Yuan Su, Chien-Lin Lee, and Kuen-Yu Tsai "A transistor sizing method for standard-cell optimization considering lithography effects", Proc. SPIE 12954, DTCO and Computational Patterning III, 129540C (10 April 2024); https://doi.org/10.1117/12.3012028

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