Patterning spacer source drain cavities in CFET devices

S. Choudhury; G. Mannaert; L. P. B. Lima; S. Demuynck; I. G. Koo; F. Lazzarino

doi:10.1117/12.3013077

9 April 2024 Patterning spacer source drain cavities in CFET devices

S. Choudhury, G. Mannaert, L. P. B. Lima, S. Demuynck, I. G. Koo, F. Lazzarino

Proceedings Volume 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII; 1295805 (2024) https://doi.org/10.1117/12.3013077
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

In conventional gate-all-around FET architecture, p-type and n-type devices are stacked on top of each other on separate devices. In Complementary FET (CFET) architecture, n-MOS and p-MOS devices are stacked in the same device on top of each other. This allows for reduction in footprint and power consumption. One of the most high aspect ratio (HAR) patterning in CFET processing comes from patterning of the gate spacer, followed by nanosheet (NSH) patterning. The HAR Spacer Source/Drain cavity area is a Si/SiGe/Dielectric superlattices bringing quite a few patterning challenges. This work discusses the challenges for the spacer opening, optimization of the profile of the source drain (SD) cavity and strategies to improve selectivity with the gate hard mask (HM). The first patterning challenge includes etching of a superlattice consisting of numerous materials, including dielectrics, while maintaining selectivity to HM. This means switching of chemistries to accommodate the patterning of these multilayers. Secondly, this patterning step needs to be highly selective to the gate HM to allow enough margin for downstream processes. The patterning step also needs to deliver vertical cavity profile. All these challenges require us to explore complex etch processes including in-situ isolation, passivation, and other etching sequences. The results and challenges for a fully patterned spacer & SD cavity as demonstrated at Imec are presented in this proceeding.

Conference Presentation

Citation Download Citation

S. Choudhury, G. Mannaert, L. P. B. Lima, S. Demuynck, I. G. Koo, and F. Lazzarino "Patterning spacer source drain cavities in CFET devices", Proc. SPIE 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, 1295805 (9 April 2024); https://doi.org/10.1117/12.3013077

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