Presentation + Paper
12 November 2024 Logic and memory patterning breakthrough using High-NA lithography
Author Affiliations +
Abstract
In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer. For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.
Conference Presentation
© (2024) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
V. M. Blanco Carballo, S. Roy, B. Chowrira, T. Pham, J. Wouters, S. Das, S. Decoster, P. Leray, R. G. Liu, K. Ronse, G. Vandenberghe, A. Niroomand, P. Foubert, V. D. Rutigliani, H. S. Suh, M. Gupta, D. de Simone, M. Dusa, C. Beral, V. Philipsen, V. Wiaux, J. H. Franke, J. Bekaert, B. Baskaran, W. Gillijns, R. H. Kim, Y. Sherazi, H. Vats, M. Cupak, C. Chang, Y.-J. Lin, J. Lee, S. Hwang, K. Yang, and K. Miyaguchi "Logic and memory patterning breakthrough using High-NA lithography", Proc. SPIE 13216, Photomask Technology 2024, 1321604 (12 November 2024); https://doi.org/10.1117/12.3047176
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KEYWORDS
Metals

Optical lithography

Logic

Semiconducting wafers

Extreme ultraviolet lithography

Etching

Scanning electron microscopy

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