Wafer level reliability

Theodore A. Dellin; William M. Miller; Donald G. Pierce; Eric S. Snyder

doi:10.1117/12.139345

14 January 1993 Wafer level reliability

Theodore A. Dellin, William M. Miller, Donald G. Pierce, Eric S. Snyder

Proceedings Volume 1802, Microelectronics Manufacturing and Reliability; (1993) https://doi.org/10.1117/12.139345
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

This paper presents a perspective on the use of Wafer Level Reliability (WLR) in developing a competitive quality/reliability program. WLR is defined as accelerated stressing of test structures at the wafer level. The pros and cons of WLR are considered in five application areas: process control; qualification; benchmarking; reliability monitoring/prediction; and modeling. WLR examples are discussed in the areas of oxide breakdown, hot carrier degradation, and electromigration. The need to develop physical, statistical, and geometrical models to extrapolate from WLR results to actual products is discussed.

Citation Download Citation

Theodore A. Dellin, William M. Miller, Donald G. Pierce, and Eric S. Snyder "Wafer level reliability", Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); https://doi.org/10.1117/12.139345

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available