Dimension-temperature combination scaling for low-temperature 0.1micron CMOS

Kazuya Masu; Michio Yokoyama; Kazuo Tsubouchi

doi:10.1117/12.221149

15 September 1995 Dimension-temperature combination scaling for low-temperature 0.1micron CMOS

Kazuya Masu, Michio Yokoyama, Kazuo Tsubouchi

Proceedings Volume 2636, Microelectronic Device and Multilevel Interconnection Technology; (1995) https://doi.org/10.1117/12.221149
Event: Microelectronic Manufacturing '95, 1995, Austin, TX, United States

Abstract

High speed and high performance is essentially required in CMOS ULSI of super workstations in the 21st century's multimedia era with every possible means. Low temperature operation of CMOS ULSI should be re- recognized for high speed application, because the low-temperature operation can always exhibit 2-3 times higher operation speed than room- temperature operation when the same design-rule microfabrication process is utilized. In this paper, we discuss a temperature scaling theory (TST) and temperature-dimension combination scaling theory (CST) for 0.1 micrometers and below-0.1 micrometers MOSFET. Emphasis of the combination scaling is that the threshold voltage and the subthreshold swing are fully scaled for low-supply voltage operation. The fabricated 77K CST-MOSFET with 1-V supply voltage has the threshold voltage (V_th) of 0.21 V and the subthreshold swing (S) of 27 mV/dec without degradation of V_th and S due to the short-channel effects.

Citation Download Citation

Kazuya Masu, Michio Yokoyama, and Kazuo Tsubouchi "Dimension-temperature combination scaling for low-temperature 0.1micron CMOS", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); https://doi.org/10.1117/12.221149

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KEYWORDS

Field effect transistors

Doping

Vestigial sideband modulation

Chlorine

Oxides

Electrons

Ions

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