Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications

H. Tian; Asanga H. Perera; D. O'Meara; H. De; C. K. Subramanian; P. Rehmann; James D. Hayden; Norm Herr

doi:10.1117/12.284616

27 August 1997 Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications

H. Tian, Asanga H. Perera, D. O'Meara, H. De, C. K. Subramanian, P. Rehmann, James D. Hayden, Norm Herr

Proceedings Volume 3212, Microelectronic Device Technology; (1997) https://doi.org/10.1117/12.284616
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

In this paper, we discuss scaled silicon bipolar transistor performance for advanced BiCMOS SRAM applications. In particular, we present experimental results of non-self aligned, single poly emitter bipolar transistors with critical dimensions scaled vertically and laterally. We demonstrate the device performance enhancement by properly scaling and show device design tradeoffs with key bipolar device parameters.

Citation Download Citation

H. Tian, Asanga H. Perera, D. O'Meara, H. De, C. K. Subramanian, P. Rehmann, James D. Hayden, and Norm Herr "Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284616

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