Built-in self-repair of VLSI memories employing neural nets

Pinaki Mazumder

doi:10.1117/12.326705

13 October 1998 Built-in self-repair of VLSI memories employing neural nets

Pinaki Mazumder

Proceedings Volume 3455, Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation; (1998) https://doi.org/10.1117/12.326705
Event: SPIE's International Symposium on Optical Science, Engineering, and Instrumentation, 1998, San Diego, CA, United States

Abstract

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Citation Download Citation

Pinaki Mazumder "Built-in self-repair of VLSI memories employing neural nets", Proc. SPIE 3455, Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation, (13 October 1998); https://doi.org/10.1117/12.326705

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KEYWORDS

Neural networks

Neurons

Very large scale integration

Evolutionary algorithms

Transistors

Yield improvement

Algorithm development

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