Fast on-line multiplication units using LSA organization

Alexandre F. Tenca; Milos D. Ercegovac; Marianne E. Louie

doi:10.1117/12.367682

2 November 1999 Fast on-line multiplication units using LSA organization

Alexandre F. Tenca, Milos D. Ercegovac, Marianne E. Louie

Proceedings Volume 3807, Advanced Signal Processing Algorithms, Architectures, and Implementations IX; (1999) https://doi.org/10.1117/12.367682
Event: SPIE's International Symposium on Optical Science, Engineering, and Instrumentation, 1999, Denver, CO, United States

Abstract

This paper presents the application of the Linear Sequential Array (LSA) retiming approach, developed for conventional digit- recurrence algorithms, to on-line multiplication. The result is a modular and fast pipelined structure which due to a small constant fan-out and cycle time independent of precision is suitable for FPGA implementation. First we present the basics of on-line multiplication, and determine data dependencies according to the LSA design methodology. Based on these dependencies we redesign the traditional on-line multiplier to obtain the LSA structure. Since in DSP applications one of the multiplier operands is fixed for a long sequence of operations, we briefly present a parallel-serial multiplication unit that receives one of the operands in parallel and the other operand in Most-Significant-Digit-First format. Performance and area results are provided for the LSA on-line multiplier design and then compared with the conventional on-line design, using Xilinx FPGAs as the target technology.

Citation Download Citation

Alexandre F. Tenca, Milos D. Ercegovac, and Marianne E. Louie "Fast on-line multiplication units using LSA organization", Proc. SPIE 3807, Advanced Signal Processing Algorithms, Architectures, and Implementations IX, (2 November 1999); https://doi.org/10.1117/12.367682

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