Mismatch characterization and modelization of deep-submicron CMOS transistors

Helene Thibieroz; Alain Duvallet

doi:10.1117/12.360542

1 September 1999 Mismatch characterization and modelization of deep-submicron CMOS transistors

Helene Thibieroz, Alain Duvallet

Proceedings Volume 3881, Microelectronic Device Technology III; (1999) https://doi.org/10.1117/12.360542
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

The characterization of nmos transistor mismatch for three different standard CMOS technologies is presented. Different methods for matching parameter extraction have been compared. By studying the correlation of these mismatch parameters, an optimized set has been generated. Using these parameters, mismatch of drain current can be predicted and modeled. The model accuracy has been studied. Finally, by comparing the mismatch model found for crucial parameters and for each technology, the impact of gate oxide thickness on mismatch characteristics has been observed.

Citation Download Citation

Helene Thibieroz and Alain Duvallet "Mismatch characterization and modelization of deep-submicron CMOS transistors", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360542

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