Paper
2 June 2003 New method for the quantitative evaluation of wafer pattern shape based on CAD data
Ryoichi Matsuoka, Masanori Takahashi, Atsushi Uemoto
Author Affiliations +
Abstract
Semiconductor device manufacturing demands rapid ramp of yield together with feature size reduction, especially for logic and ASIC because of their short-lives and small volume production characteristics. As a technological breakthrough for rapid yield ramp of such devices, we have endeavored to integrate CAD technology with SEM for printed pattern observation, and have developed Grade Scope, an evaluation technology, by combining the wafer proces and upstream design process.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ryoichi Matsuoka, Masanori Takahashi, and Atsushi Uemoto "New method for the quantitative evaluation of wafer pattern shape based on CAD data", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); https://doi.org/10.1117/12.483688
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CITATIONS
Cited by 5 scholarly publications.
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KEYWORDS
Computer aided design

Scanning electron microscopy

Lithography

Semiconducting wafers

Manufacturing

Optical proximity correction

Semiconductors

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