A tri-mode 802.11 baseband PHY mixed signal integrated circuit in 0.13-um CMOS

Philip J. Ryan; Brian Hart; Mike Webb; Kevin Wong

doi:10.1117/12.531439

30 March 2004 A tri-mode 802.11 baseband PHY mixed signal integrated circuit in 0.13-μm CMOS

Philip J. Ryan, Brian Hart, Mike Webb, Kevin Wong

Proceedings Volume 5274, Microelectronics: Design, Technology, and Packaging; (2004) https://doi.org/10.1117/12.531439
Event: Microelectronics, MEMS, and Nanotechnology, 2003, Perth, Australia

Abstract

A 0.13um CMOS mixed signal 802.11a/b/g baseband PHY IC, with per-packet receive diversity, 802.11h radar/DFS support and an MRC/MIMO coprocessor interface, is described. Required receive C/N is 5dB at 6 Mbps, and 20dB at 54 Mbps. Residual packet error rate is less than 4% for 54 Mbps and 0.1% for 6 Mbps link data rates in a 50ns delay spread channel. The 4.75×4.75mm chip, fabricated in 1P7M 0.13um CMOS, has 8M transistors and dissipates under 31mW in sleep, 206mW in Tx, and 362mW in Rx.

Citation Download Citation

Philip J. Ryan, Brian Hart, Mike Webb, and Kevin Wong "A tri-mode 802.11 baseband PHY mixed signal integrated circuit in 0.13-μm CMOS", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); https://doi.org/10.1117/12.531439

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