Architecture for dynamically reconfigurable real-time lossless compression

Alison J Carter; Neil C Audsley

doi:10.1117/12.526484

18 May 2004 Architecture for dynamically reconfigurable real-time lossless compression

Alison J Carter, Neil C Audsley

Proceedings Volume 5297, Real-Time Imaging VIII; (2004) https://doi.org/10.1117/12.526484
Event: Electronic Imaging 2004, 2004, San Jose, California, United States

Abstract

Image compression is a computationally intensive task, which can be undertaken most efficiently by dedicated hardware. If a portable device is to carry out real-time compression on a variety of image types, then it may be useful to reconfigure the circuitry dynamically. Using commercial off-the shelf (COTS) chips, reconfiguration is usually implemented by a complete re-load from memory, but it is also possible to perform a partial reconfiguration. This work studies the use of programmable hardware devices to implement the lossless JPEG compression algorithm in real-time on a stream of independent image frames. The data rate is faster than can be compressed serially in hardware by a single processor, so the operation is split amongst several processors. These are implemented as programmable circuits, together with necessary buffering of input and output data. The timing of input and output, bearing in mind the different, and context-dependent amounts of data due to Huffman coding, is analyzed using storage-timing graphs. Because there may be differing parameters from one frame to the next, several different configurations are prepared and stored, ready to load as required. The scheduling of these reconfigurations, and the distribution/recombination of data streams is studied, giving an analysis of the real-time performance.

Citation Download Citation

Alison J Carter and Neil C Audsley "Architecture for dynamically reconfigurable real-time lossless compression", Proc. SPIE 5297, Real-Time Imaging VIII, (18 May 2004); https://doi.org/10.1117/12.526484

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