Embedded design-for-testability strategies to test high-resolution SD modulators

Sara Escalera; Alvaro Espin; Oscar Guerra; Jose M. de la Rosa; Fernando Medeiro; Belen Perez-Verdu

doi:10.1117/12.608301

30 June 2005 Embedded design-for-testability strategies to test high-resolution SD modulators

Sara Escalera, Alvaro Espin, Oscar Guerra, Jose M. de la Rosa, Fernando Medeiro, Belen Perez-Verdu

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608301
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

This paper describes the design-for-testability strategies integrated in a 0.35μm CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented. Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.

Citation Download Citation

Sara Escalera, Alvaro Espin, Oscar Guerra, Jose M. de la Rosa, Fernando Medeiro, and Belen Perez-Verdu "Embedded design-for-testability strategies to test high-resolution SD modulators", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608301

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