In-chip overlay metrology

Y. S. Ku; C. H. Tung; Y. P. Li; H. L. Pang; N. P. Smith; L. Binns; T. Rigden; G. Reynolds; H. Fink

doi:10.1117/12.655953

24 March 2006 In-chip overlay metrology

Y. S. Ku, C. H. Tung, Y. P. Li, H. L. Pang, N. P. Smith, L. Binns, T. Rigden, G. Reynolds, H. Fink

Proceedings Volume 6152, Metrology, Inspection, and Process Control for Microlithography XX; 615214 (2006) https://doi.org/10.1117/12.655953
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

The feasibility of measuring overlay using small targets has been demonstrated in an earlier paper¹. If the target is small ("smallness" being relative to the resolution of the imaging tool) then only the symmetry of its image changes with overlay offset. For our purposes the targets must be less than 5μm across, but ideally much smaller, so that they can be positioned within the active areas of real devices. These targets allow overlay variation to be tested in ways that are not possible using larger conventional target designs. In this paper we describe continued development of this technology. In our previous experimental work the targets were limited to relatively large sizes (3x3μm) by the available process tools. In this paper we report experimental results from smaller targets (down to 1x1μm) fabricated using an e-beam writer. We compare experimental results for the change of image asymmetry of these targets with overlay offset and with modeled simulations. The image of the targets depends on film properties and their design should be optimized to provide the maximum variation of image symmetry with overlay offset. Implementation of this technology on product wafers will be simplified by using an image model to optimize the target design for specific process layers. Our results show the necessary good agreement between experimental data and the model. The determination of asymmetry from the images of targets as small as 1μm allows the measurement of overlay with total measurement uncertainty as low as 2nm.

Citation Download Citation

Y. S. Ku, C. H. Tung, Y. P. Li, H. L. Pang, N. P. Smith, L. Binns, T. Rigden, G. Reynolds, and H. Fink "In-chip overlay metrology", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 615214 (24 March 2006); https://doi.org/10.1117/12.655953

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