Challenges and solutions for trench lithography beyond 65nm node

Zhijian Lu; Chi-Chien Ho; Mark Mason; Andrew Anderson; Randy Mckee; Ricky Jackson; Cynthia Zhu; Mark Terry

doi:10.1117/12.659242

14 March 2006 Challenges and solutions for trench lithography beyond 65nm node

Zhijian Lu, Chi-Chien Ho, Mark Mason, Andrew Anderson, Randy Mckee, Ricky Jackson, Cynthia Zhu, Mark Terry

Proceedings Volume 6156, Design and Process Integration for Microelectronic Manufacturing IV; 615617 (2006) https://doi.org/10.1117/12.659242
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

Due to complex interconnect wiring scheme and constraints from process rules, systematic defects such as pattern necking and bridging are a major concern for metal layers. These systematic defects or "weak spots" can be major yield detractors in IC manufacturing if not properly addressed. These defects can occur even in cases where model-based OPC has been implemented, as well as a variety of process rules for margin insurance. Determining how to improve the marginalities or "weak spots" becomes a key factor for enhancing product yields. This paper will address several root causes for pattern induced defects and present solutions to a variety of weak spots including "T-shape," "H-shape," "Thin-Line," and "Bowling Pin" defects during 65nm product development at TI. Through case studies, we demonstrate how to successfully provide DFM (Design for Manufacturing) by using Resolution Enhancement Techniques (RET) tools to avoid and minimize the weak spots. Furthermore, process techniques to improve printability for some of the weak spots as applied to 65nm reticle sets will be discussed. An integrated scheme aiming at optimization of design rules and process rules is proposed.

Citation Download Citation

Zhijian Lu, Chi-Chien Ho, Mark Mason, Andrew Anderson, Randy Mckee, Ricky Jackson, Cynthia Zhu, and Mark Terry "Challenges and solutions for trench lithography beyond 65nm node", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615617 (14 March 2006); https://doi.org/10.1117/12.659242

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