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Model-based hotspot detection and silicon-aware parametric analysis help designers optimize their chips for yield,
area and performance without the high cost of applying foundries' recommended design rules. This set of DFM/
recommended rules is primarily litho-driven, but cannot guarantee a manufacturable design without imposing overly
restrictive design requirements. This rule-based methodology of making design decisions based on idealized
polygons that no longer represent what is on silicon needs to be replaced. Using model-based simulation of the
lithography, OPC, RET and etch effects, followed by electrical evaluation of the resulting shapes, leads to a more
realistic and accurate analysis. This analysis can be used to evaluate intelligent design trade-offs and identify
potential failures due to systematic manufacturing defects during the design phase.
The successful DFM design methodology consists of three parts:
1. Achieve a more aggressive layout through limited usage of litho-related recommended design rules.
A 10% to 15% area reduction is achieved by using more aggressive design rules. DFM/recommended
design rules are used only if there is no impact on cell size.
2. Identify and fix hotspots using a model-based layout printability checker.
Model-based litho and etch simulation are done at the cell level to identify hotspots. Violations of
recommended rules may cause additional hotspots, which are then fixed. The resulting design is ready for
step 3.
3. Improve timing accuracy with a process-aware parametric analysis tool for transistors and interconnect.
Contours of diffusion, poly and metal layers are used for parametric analysis.
In this paper, we show the results of this physical and electrical DFM methodology at Qualcomm. We describe how
Qualcomm was able to develop more aggressive cell designs that yielded a 10% to 15% area reduction using this
methodology. Model-based shape simulation was employed during library development to validate architecture
choices and to optimize cell layout. At the physical verification stage, the shape simulator was run at full-chip level
to identify and fix residual hotspots on interconnect layers, on poly or metal 1 due to interaction between adjacent
cells, or on metal 1 due to interaction between routing (via and via cover) and cell geometry.
To determine an appropriate electrical DFM solution, Qualcomm developed an experiment to examine various
electrical effects. After reporting the silicon results of this experiment, which showed sizeable delay variations due
to lithography-related systematic effects, we also explain how contours of diffusion, poly and metal can be used for
silicon-aware parametric analysis of transistors and interconnect at the cell-, block- and chip-level.
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