FPGA design of MOMS-based sampling rate converters

Uwe Meyer-Bäse

doi:10.1117/12.777231

3 April 2008 FPGA design of MOMS-based sampling rate converters

Uwe Meyer-Bäse

Proceedings Volume 6979, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks VI; 697906 (2008) https://doi.org/10.1117/12.777231
Event: SPIE Defense and Security Symposium, 2008, Orlando, Florida, United States

Abstract

In this paper we describe design options when implementing sampling rate converters with FPGAs. We first review typical designs using IIR and FFT-based systems and then show implementations of fractional sampling rate changer ranging from Lagrange, B-spline to recently introduced C-MOMS and O-MOMS designs. Speed, area and error performance results for the circuits designed in VHDL are provided.

Citation Download Citation

Uwe Meyer-Bäse "FPGA design of MOMS-based sampling rate converters", Proc. SPIE 6979, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks VI, 697906 (3 April 2008); https://doi.org/10.1117/12.777231

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