Paper
1 April 2009 Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes
Author Affiliations +
Abstract
As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Steven Holmes, Chiew-Seng Koay, Karen Petrillo, Kuang-Jung Chen, Matthew E. Colburn, Jason Cantone, Kenichi Ueda, Andrew Metz, Shannon Dunn, Youri van Dommelen, Michael Crouse, Judy Galloway, Emil Schmitt-Weaver, Aiquin Jiang, Robert Routh, Cherry Tang, Mark Slezak, Sumanth Kini, and Tony DiBiase "Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 727305 (1 April 2009); https://doi.org/10.1117/12.828483
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Cited by 4 scholarly publications.
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KEYWORDS
Overlay metrology

Semiconducting wafers

Double patterning technology

Lithography

Semiconductors

Defect inspection

Scanning electron microscopy

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