Paper
12 December 2009 Litho scenario solutions for FinFET SRAM 22nm node
Author Affiliations +
Proceedings Volume 7520, Lithography Asia 2009; 752025 (2009) https://doi.org/10.1117/12.837495
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan
Abstract
For the development of the most cost effective lithographic solutions for the 22nm node, the lithographic process and relevant requirements on CDU and overlay need to be identified. In this work, 22nm logic SRAM is selected as use case because FinFET SRAM cells are considered to be a potential successor to conventional planar transistors for 22nm node chips. We focus on the back-end layers of FinFET SRAM, including metal and contact. Litho solutions simulated under ideal scanner conditions with the ASML Brion TachyonTM SMO product are shown. This tool co-optimizes a pixilated freeform source and a continuous transmission gray tone mask based on merit functions of edge placement error. Per scenario, these simulations result in a set of preferred litho solutions with respective source and mask. These solutions have to comply with an imaging metric characterized by MEEF and common PW based on typical fab requirements. In a second step the previously generated solutions are evaluated for CDU analysis using realistic scanner error budget. The purpose is to predict the CDU performance of scanner, process and reticle in order to identify the major contributors for every scenario solution.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Shih-En Tseng, Shun-Der Wu, Jacques Wang, Jay Kou, Orion Mouraille, Reiner Jungblut, Tsann-Bim Chiou, Jo Finders, Alek Chen, Mircea Dusa, and Stephen Hsu "Litho scenario solutions for FinFET SRAM 22nm node", Proc. SPIE 7520, Lithography Asia 2009, 752025 (12 December 2009); https://doi.org/10.1117/12.837495
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KEYWORDS
Source mask optimization

Scanners

Photomasks

Reticles

Diffractive optical elements

Double patterning technology

Etching

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