New method of SOC clock design based on hierarchical mode

Dandan Wang

doi:10.1117/12.913475

1 October 2011 New method of SOC clock design based on hierarchical mode

Dandan Wang

Proceedings Volume 8285, International Conference on Graphic and Image Processing (ICGIP 2011); 82856F (2011) https://doi.org/10.1117/12.913475
Event: 2011 International Conference on Graphic and Image Processing, 2011, Cairo, Egypt

Abstract

The new problems of traditional clock design in hierarchical mode were analyzed in this paper and a new method of clock design was proposed. A phase_sync signal was used as a bridge of top-level and sub-design in this method. It effectively prevents the 'damage' to the internal timing of sub-design caused by top-level timing closure. The application of this method avoids reset design of clock divider circuit and reduces the difficulty of physical design

Citation Download Citation

Dandan Wang "New method of SOC clock design based on hierarchical mode", Proc. SPIE 8285, International Conference on Graphic and Image Processing (ICGIP 2011), 82856F (1 October 2011); https://doi.org/10.1117/12.913475

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