Resistive shorts characterization in CMOS standard cells for test pattern generation

Andrzej Wielgus; Bartosz Potrykus

doi:10.1117/12.2031300

25 July 2013 Resistive shorts characterization in CMOS standard cells for test pattern generation

Andrzej Wielgus, Bartosz Potrykus

Proceedings Volume 8902, Electron Technology Conference 2013; 89020W (2013) https://doi.org/10.1117/12.2031300
Event: Electron Technology Conference 2013, 2013, Ryn, Poland

Abstract

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.

Citation Download Citation

Andrzej Wielgus and Bartosz Potrykus "Resistive shorts characterization in CMOS standard cells for test pattern generation", Proc. SPIE 8902, Electron Technology Conference 2013, 89020W (25 July 2013); https://doi.org/10.1117/12.2031300

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