Optoelectronically interconnected hardware-efficient deep learning using silicon photonic chips

Chenghao Feng; Jiaqi Gu; Hanqing Zhu; Zhoufeng Ying; Zheng Zhao; David Z. Pan; Ray T. Chen

doi:10.1117/12.2616217

5 March 2022 Optoelectronically interconnected hardware-efficient deep learning using silicon photonic chips

Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David Z. Pan, Ray T. Chen

Proceedings Volume PC12007, Optical Interconnects XXII; PC1200702 (2022) https://doi.org/10.1117/12.2616217
Event: SPIE OPTO, 2022, San Francisco, California, United States

Abstract

Deep neural networks (DNNs) have shown their superiority in a variety of complicated machine learning tasks. However, large-scale DNNs are computation- and memory-intensive, and significant efforts have been made to improve the efficiency of DNNs through the use of better hardware accelerators as well as software training algorithms. The optical neural network (ONN) is a promising candidate as a next-generation neurocomputing platform due to its high parallelism, low latency, and low energy consumption. Here, we devise a hardware-efficient optical neural network architecture named optical subspace neural network (OSNN), which targets lower optical component usage, area cost, and energy consumption of previous ONN architectures with comparable task performance. Additionally, a hardware-aware training framework is provided to minimize the required control precision, lessen the chip area, and boost the noise robustness.

Conference Presentation

Citation Download Citation

Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David Z. Pan, and Ray T. Chen "Optoelectronically interconnected hardware-efficient deep learning using silicon photonic chips", Proc. SPIE PC12007, Optical Interconnects XXII, PC1200702 (5 March 2022); https://doi.org/10.1117/12.2616217

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