The transition from finFETs to nanosheet transistors is on. The industry is therefore looking into the options for a subsequent device, among which forksheet transistors appear as a serious contender [1]. Common to the processing of these Gate-All-Around architectures, the cavity etch, wherein SiGe is etched laterally from a SiGe/Si multilayer, remains a step of paramount importance [2]. Its development therefore requires new techniques for geometrical and material characterization.
In this paper, we elaborate on the use of top-down spectroscopic techniques [3] to measure critical parameters such as cavity depth, stress and SiGe residues in nanosheet and forksheet transistors.
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