The answer of Failure Analysis (F/A) to the technological innovations in microelectronics in the past was: with a slight evolution (i.e. optical microscope -- SEM -- TEM) we can do it. The innovations around the corner today enforce a paradigm shift in F/A to match the challenges by increasing wafer sizes, decreasing feature sizes and new package concepts. This presentation highlights various aspects of the small feature size time bomb (how TEM becomes mandatory and obsolete synchronously), the completely new inline F/A approach on productive wafers inevitable from 300 nm wafer size on, and the reinvention of electrical fail site localization techniques, now from the backside of the die due to new package concepts and innumerable metal layers. Even if F/A manages to overcome all these challenges from a technical point of view, the according revolution in terms of methods, skills and tools implies a cost explosion unless F/A becomes an active part in the business process and the projects of development and manufacturing. This holds even under the assumption that a rising number of today's F/A problems will be solved by modern testing techniques. Only this way F/A can deliver custom-tailored solutions that are optimized in productivity and time to result, and that fulfill the cost reduction requirements of semiconductor products.

As IC device dimensions get smaller and smaller, not only do the formation and nature of silicide on the active silicon area become increasingly critical but so does the need for silicide inspection. The ability to inspect the silicide itself is especially important at electrical failure sites. In this paper we describe a straightforward sample preparation method which enables us, after removal of the substrate, to observe silicide from the back side using a scanning electron microscope (SEM). This method was used in combination with photo-emission microscopy (PEM) to localize the exact site of leaky junctions. With this method the silicide grains of different phases can easily be observed over large areas. It was found that in the leaking sites only the large grain C54 phase of TiSi₂ was present and never the small grain C49 phase. In this paper we explain junction leakage in connection with phase transformation of titanium silicide, and show that the C54 phase which is normally desired for its low resistance may be problematic when the active Si areas are very small or when the titanium layer thickness is too thin. We also demonstrate that this method makes gate oxides, contact misalignment and other front-end issues readily observable.

Modern dual beam SEM/FIB tools will allow physical failure analysis on productive wafers in the cleanroom if contamination of wafer and production equipment can be controlled. In this study we show that the risks of Ga- diffusion and -desorption as well as heavy metal contamination can be overcome. The reentry of analyzed wafers into the production flow results in lower overall costs and a dramatically shortened feedback loop to production engineers, leading to reduced down times of production tools etc. Most FIB-applications (i.e. highlight etch of cross sections) can be processed with appropriate gas chemistry. Ion Beam deposition of an insulating material to refill the crater created by the sputtering process is also investigated. If either resolution is not sufficient or more complex analyses have to be applied a sample lift-out technique was developed making it obsolete to sacrifice wafers also in these cases. The fixed sample can be analyzed off-line with all PFA- methods, even plasma etching or lift-off in HF is possible. The benefits of this quantum leap for physical failure analysis are reduction of wafer costs and the possibility to reduce analysis cycle time as well as the number of learning cycles in technology development.

In recent years, scanning acoustic microscopy (SAM) has been found to be a very successful technique when used in the microelectronics industry to evaluate, from a reliability perspective, standard plastic packaging technologies such as PQFP's, PLCC's, DIP's and SOP's. The recent explosion of advanced packaging techniques such as Chip-on-Board, Flip-chip and BGA and the proliferation of Microsystems has further widened the arena of what constitutes microelectronics. With such a wide breadth of devices from standard plastic packages to state-of-the-art microsystems, it is difficult to find a failure analysis technique which can cope competently with that scope. SAM is one such technique. This paper will demonstrate the effectiveness of SAM at non-destructively analyzing a range of advanced packaging technologies from integrated passive to flip-chip to microsystems.

The mechanism of planarization wrinkle defect in complementary metal oxide semiconductor (CMOS) color filter process is discussed in this paper. The wrinkle phenomena occurred as the planarization resist thickness decreased and became worse after high temperature baking was implemented. In experiment, the effect of factors on the wrinkle with KLA scanning such as resist thickness, soft bake temperature and time after resist coating and development puddle time were analyzed. From the data, the wrinkle is connectable with the developer penetration into and break through the resist film. Some solutions can be applied to solve this problem. Strengthening the resist film by increasing expose energy to get higher degree of polymerization is the best solution. Increasing resist thickness also can inhibit wrinkle but it is limited by the overall stack height for optimizing microlens focal length. Prolonging the soft bake time and reducing the puddle time of development to eliminate the penetration effect of developer are not obvious.

The increased interest in epitaxial Si_1-xGe_x/Si heterostructures for device applications requires very good control of layer thickness and composition. Unfortunately, most of the well-developed characterization methods such as Rutherfored Backscattering Spectroscopy, Secondary Ion Mass Spectroscopy, and Photoluminescence measurements are unsuitable as production measurement tools. On the contrary, Spectroscopic Ellipsometry allows a fast, in-line and non- destructive analysis, including wafer mapping facilities. This paper demonstrates the suitability of Spectroscopic Ellipsometry for the determination of both Ge content and layer thickness of epitaxial Si_1-xGe_x for Ge contents between 1 and 36%. By describing the optical dispersion by means of the harmonic oscillator model, we obtained a clear correlation between the Ge content and E_n(1), the resonant energy of the first oscillator, and n_max, the peak value of the real part of the refractive index. The small spot (28 X 14 micrometer²) size allows to analyze Si_1-xGe_x layers grown in an isolation structure. The small window size prevents Rutherford Backscattering Spectroscopy measurements. Spectroscopic Ellipsometry allowed the fine tuning of selective and non-selective epitaxial growth processes with regard to growth rate, Ge incorporation and wafer uniformity. Furthermore, Spectroscopic Ellipsometry might be capable to extract separate thicknesses of more complex structures. This was successfully applied on Si capped Si_1-xGe_x layers.

In this article, we emphasize the streamlined, in-line inspection methodology at Agere Systems, Madrid, Spain (formally Lucent Technologies, Microelectronics). This method includes the use of AIT-II with Impact ADC 2.0 to better focus and separate out excursion and baseline events. Real life examples demonstrating the potential of ADC are presented. In continuation, the shop reaction methodology and data flow scheme is described in detail. Currently, the Agere systems methodology is one of the most advanced in the European semiconductor industry.

Surface Charge (SCA), is an electro-optical method which allows for immediate and non-destructive characterization of the electronic properties of the semiconductor/insulator system. Unlike conventional capacitance techniques it does not require formation of a gate electrode and direct electrical contacts. It determines the electronic properties of the system from surface photovoltage measurements of the depletion layer width as a function of an external electric field. The method allows for determination of the dielectric (oxide) charge, energy distribution of the interface trap density, doping type and doping concentration at the semiconductor surface. Capabilities of the SCA technique extend from the bare surface to several microns thick dielectric coatings. These are demonstrated for Si wafers in such applications as dry and wet cleaning, oxidation and deposition processes.

The adjustment of bonding parameters has been based for long time exclusively on the results of pull- and shear tests. Observing these parameters to be too low, bondparameters have been usually adjusted towards a stronger direction. FIB characterization, however, has shown, that in many cases pull forces have been at a low level, because the top chip metal layer (aluminum) has been completely consumed by the bondball- gold, forming a thick intermetallic phase with only weak adhesion to the barrier layer or intermetal dielectric. In these cases, reduction of the bonding parameters would be the suitable corrective action, whilst stronger adjustment results in cracking the silicon device or local cratering. Using different adjustments of bonding parameters, the point of optimum could be well found, corrected by the results of FIB- cross-sectional characterization. A good corresponding between cross-section analysis results and bonding process parameters has been found. It gives valuable hints on both process- homogeneity over the whole bonding length as well as on the optimum of the intermetallic layer thickness, which still should leave a continuous layer of chip metal. The border extremes show at one end of the process window local weak bonding and delamination lines, at the other end a completely consumed chip metallization. FIB characterization shows the bonding process influence on the grain structure of both wire and chip metallization, too.

X-ray laminography is a method that allows getting local depth information from big flat objects like PCBs and electronic assemblies. The few X-ray laminography systems recently introduced on the market cannot reach the spatial resolution that is necessary for inspection of modern electronic assemblies. According to the needs in high-resolution inspections for electronic industry a digital X-ray microlaminography system has been developed on the base of multilayer tomosynthesis approach. This instrument is based on the new x-ray geometry with minimum moving parts. It can reach a spatial resolution of several microns in plane and in depth and visualize layer-by-layer area of 5 X 5 mm at any place in an object up to several hundreds mm in size. Typical scanning time is 20 seconds for 20 layers and 90 seconds for 100 layers. The software package includes the system control and multilayer tomosynthesys (layer-by-layer separation) during acquisition, as well as a three-dimensional rendering program for realistic visualization of the object's microstructure. The main application areas are BGA inspection, Flip-Chips, multilayer PCBs, micromechanics (watch, etc.).

Today laser beam soldering (LBS) is a non-standard manufacturing process for electronic packaging and interconnection technology. However due to the onwardly going miniaturization and the world-wide trend towards lead-free solders LBS gains more attention for certain applications in this field. In mass-production, e.g. in interconnection technology of electronic devices, it is state-of-the-art to use solder alloys in the form of paste. Today it is a well- known process to handle or to deposit solder paste. Furthermore the composition of solder systems, consisting of metal alloys and fluxes, can be optimized for individual products and production conditions. Yet this optimization process is only in part performed for LBS with solder paste. Therefore the application of standard reflow solder pastes for LBS poses problems like gas eruptions, solder balling and overheating. In order to overcome these quality problems an adapted time-power-profile for LBS with solder paste has been developed, using synchronized high-speed photography and detection of secondary emissions from the joining area. The evaluation of the experiments allows the generation of high quality solder joints with standard diode laser systems and solder pastes. In addition it is possible to realize an online-process control via detecting the secondary emissions from the subsequent transformation stages of the solder paste. Conclusively it can be said LBS is a stable, reproducible process for applications requiring a controlled locally limited heat input and reduced thermal and mechanical stress compared to conventional techniques.

We present a summary of the recent advances in endpoint and in-line monitoring techniques for chemical-mechanical polishing (CMP) processes. We discuss the technical challenges and review some of the approaches that have been published and/or patented. These methods include optical, thermal (pad temperature), friction (torque motor current), electrochemical, chemical, electrical, and acoustic (vibration). We also present experimental data obtained in our laboratory using selected endpoint methods for metal and oxide CMP.

SOI devices have been shown to present better performances as compared to Bulk MOSFETs for low power-low voltage IC's. Thick film partially depleted SOI transistors have mainly been proposed up to now. However, for 0.1 and sub-0.1 micrometer devices or ultra low power devices, fully depleted thin and ultra-thin SOI MOSFETs with recess channel seem to be the best candidates. Indeed, those devices have been shown to present interesting properties in term of short channel effects, subthreshold swing and electron temperature. But one of the major bottleneck of SOI devices is the final film thickness control. According to the Lim and Fossum long channel model, the front interface threshold voltage is linearly dependent with the doping and the final silicon film thickness. Cumulative fluctuations of oxide growths and the non self alignment of the gate induce a strong threshold voltage variation on wafer and on a whole run. According to experimental results and 2D simulations the impact of the film thickness fluctuations and gate misalignment on the electrical performance will be presented. The maximum variations allowed to reach the design specifications will be extracted and finally a process windows will be defined.

We show that a simple post-stress test can provide a good early reliability indicator. The defect types that have been revealed by this post-stress test are two types of conductive particles on metal levels. This early indicator has been of great value when dealing with potentially contaminated wafers/lots and to evaluate and to prioritize the corrective actions to solve the line issues.

We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer² in sizes. Both positive and quasi-negative photoresists were employed. The resultant products are holes in the developed positive photoresist layer and mushroom- shaped spots in the quasi-negative one. Based on the photoresist decomposition energy dose, we could approximately calculate the light emitting power in the near UV range. Due to the proximity between the layer and the light source, the power is interpreted on a more accurate basis, which was a difficult task in previous research. The product sizes, dependent on the light emitting currents and exposure time, establish the core for a rough model that can be used for further application of this technique as a reliability analysis tool. One potential application is to detect and characterize regions of hot carriers on a VLSI circuit under operation for design improvement purpose.

Ionic contamination in microelectronic circuitry can have a detrimental effect on device reliability and yield. Post- aluminum etch corrosion has been considered a critical issue in dry plasma etching of aluminum. In this work, we review the actions taken to reduce the amount of defects due to Cl- induced corrosion in the metal lines at our manufacturing line in Lucent Technologies Madrid. Two approaches were followed in a parallel way: on one side manufacturing procedures were modified to reduce at the minimum the exposure of the unprotected metal lines to the clean room environment thus it is avoided any metal corrosion caused by a possible environmental contamination. The second working line was to improve the resistance to corrosion of the post-etched metal. With this aim, our efforts were focused on the passivation step just after the metal etch and prior the photoresist strip. The influence of several parameter settings of the passivation plasma on the resistance of the etched metal to corrosion has been studied. Accelerated corrosion tests were used to monitor the intrinsic metallization susceptibility of corrosion and chlorine and fluorine residuals content in the wafer were measured using ion-chromatography. It was found that a modification in the pressure, plasma power or duration of the passivation step could have a beneficial impact on the amount of chlorine residues left on the metal lines after etch and consequently an enhancement of their resistance to corrosion.

This paper examines using an optical endpoint system to control over etching of a complex spacer such as the L-shaped spacer. The endpoint detection system (EPD 202) was used to monitor the etch chemistry on the TEL Unity II e plasma etcher. EPD202 monitors the chemistry change at the top tetraethylorthosilicate (TEOS)/nitride interface and the underlying nitride/TEOS interface. Therefore, a plasma change (film change) is detected twice by the EPD202 monitoring system. This optical double endpoint algorithm reduces the possibility of over etching the layers regardless of the incoming film variations. Verification of module improvement using the endpoint algorithm, instead of the time etch, was collected by inline Tencor 1270 TUV measurements and Scanning Electron Microscope (SEM) cross-sections. The EPD202 system improved etch uniformity by 44%, thereby implying an increase in the repeatability of the gate spacer and overall reliability of the product.

A methodology is described which establishes the prioritization of defects based on electrical impact of the different defect types using a Short Loop Yield Monitor under conditions of low statistics. Probe results from specifically designed test patterns for interconnect structures are correlated with optical defect inspection data to determine the kill rates of various defects. The results provide quantitative means to rank the importance of defects as well as the effectiveness of the inspection strategy. The wafers are optically inspected at each process step and reviewed with an automated SEM (SEMVision). The defects are tracked and a defect Pareto is established. After final processing, the electrical testing is performed and correlations are established. The defects are ranked by a quantitative approach based on the kill rate. A unique and important feature of the approach is to use deliberately introduced defects to study the impact at specific process points. The use of controlled defect introduction allows an improved statistical analysis for low coverage inspection plans. It appears that particles that occur at early stages in the process have an enhanced impact because of a potential size amplification effect. With the impact quantified, effective inspection and defect reduction plans can be implemented.

The dislocation at the trench corner under Poly mask edges was found to be the major killer of junction leakage in generic logic technology. The impact of the sacrificial oxide (SAC-OX) of the well ion implantation (I/I) module and the source/drain (S/D) I/I to the defect formation are investigated for the first time. The influence on N⁺/P-Well junction leakage caused by the I/I sacrificial oxide from the Rapid Thermal Oxidation (RTO) and Furnace Oxidation (FO) are evaluated by using the process monitoring test structures. Based on the analysis of test structures and the yield evaluation of product, the optimized condition is proposed.

Defects in semiconductor industry become more important by shrinking structures and increasing complexity of process. Therefore the size of a killer defect becomes smaller and it is not easy to find them with optical inspection tools. In addition Inspection tools are not able to say something about electrical effects from defects which are found. With Checkerboard Test Structures it is possible to locate electrical defects. In fact these special test structures will be tested at the end of the process, like an usual function test. A special developed algorithm allows low quantity of pads. This gives a high spatial resolution and on the other hand we have good ratio between active and passive area. A reduction of a statistical failure could be reached, because it is not necessary to calculate the defect density from a small region. In particular special defect distribution like cluster can be considered. With this structures different layers can be examined for disconnections and short-circuits. Therefore it is possible to locate defects in one layer or between two layers. So the defect density for the sensitive dielectrica between two layers, like any kind of oxide can be calculated. The karree test structures can be used very good as an inline-defectmonitoring, because there is no difference from the original technology of proces. There are also no differences in time for processing and for testing, so Karreeteststructures is an optimal representation for your process.

In-line reaction to defect excursions is becoming critical to the semiconductor fabs to achieve competitive advantages by maintaining good learning curves. Traditional reaction techniques are based on the SPC methodology applied to process variables and data provided by the inspection tools, like defect counts by layer or classified defects (either manually or by ADC). But all these techniques lack from a fundamental information: the killing potential of the variables under control. Many times, 'out of control' processes mean no yield loss, whereas small deviations in 'in-control' processes can cause severe damage. We present a methodology to achieve in- line reaction based on combining predictive yield loss calculation for the lots currently being processed and SPC methodology. This analysis method opens a new perspective for the in-line reaction tools and provides a way to reduce dramatically the amount of yield excursions.

Physical failure analysis on inspected and bitmapped wafers prove a compelling way to pareto defect sources on memory products. Failure analysis also indicates the relationship between the electrical signature (row, column etc.) and the physical layer (gate, metal-0, etc.) Failure analysis very rarely, however, shows a one-to-one relationship between defects and electrical signatures. Electrical signatures can correspond to different defect sources: a double-bit failure might indicate either a blocked common-source contact or cell- to-cell leakage. Likewise, foreign material at the gate level might cause a cross failure if shorted to a contact, or a row failure if shorted to another gate. Yield engineers have developed algorithms to quantify the relationship between inline defects and electrical signatures; commercially available semiconductor-specific software can do the same. Although varying in their capability, these tools answer following questions: given that a die has a particular electrical signature, what is the most likely source of the defect? And given that a die has a defect at a certain level, what electrical signature will this most likely cause? Bayes' theorem can provide an answer to both. We apply Bayes' theorem to show the relationship between a sample of physical defects and electrical signatures on a DRAM product.

An important point in the in-line yield improvement strategy is to be able to react as soon as possible to the alarms detected, and stop the excursions quickly in order to reduce the impact in yield loss and reliability. Therefore, to improve these requirements, we have developed a procedure, using web-based tools, which we detail in this paper. This exchange of information system permits the operators to easily access the engineer's documents. The engineering expertise about the usual problems is concentrated in these documents, which clearly explains the procedures to follow. Using a web interface, operators can complete all necessary data to continue with the investigation through different shifts. This database is easily accessible by engineers and other operators and the information is structured and organized in a uniform and correct way. In this paper we will show the benefits that we have found during the last six months working in production with this procedure.

In this article, we describe the experiments and analysis of a contamination caused defect, which only appears after the polysilicon gate deposition process of a CMOS semiconductor chip. The polysilicon defects are about 0.3 micrometer in diameter. The defects appear densely in one area of the wafer and they closely resemble the phosphorous contaminate defect, although no analysis method could detect the element(s). The most notable characteristic is the defect density, which varies with the different areas within a chip. There are several common conditions which are notable. First, the defect only occurs in 3V technology. Secondly, the defect occurs where the gate oxidation boat contacts the wafer. The most notable experiment was the rotation of the wafers in the gate oxidation, processing step. The wafers were rotated about 20 degrees before they were loaded into the boats and the poly bump defect area also moved about 20 degrees. Thirdly, the defect occurs sporadically with no relation to common process tools or maintenance. Recently, the gate oxidation process was changed from horizontal to vertical furnaces and since this change there has not been any poly bump defects event.

For better resolution and throughput concern on color filter process, we use ASML5500/100 for color filter production instead of 1X CANON, but it often suffered alignment fail (error code: model error) at the green layer. Some items have been studied: (1) pattern close to ASML PM mark; (2) level sensor issue (level sensor contamination, plate tilt, level lens contamination); (3) different process sequence; (4) open the clear-out window at passivation layer to reduce interference effect. All of these items are proved no obviously influence to induce model error. By checking the spectrum of the green photo-resist, we found that it is low transmittance at 633 nm¹ (the wavelength that the ASML alignment laser uses). Raising the transmittance by reducing the thickness of green resist is proved useful to eliminate the occurrence of model error. On the other hand, the ATHENA^TM provided by ASML which use red and green lights for alignment will get rid of the alignment failure.

The combined influence of irradiation and thermal treatment upon efficiency of formation of stable radiation defects in silicon diffusion diodes was studied by DLTS and measurements of transient characteristics. High-temperature (300 - 450 degrees Celsius) irradiation by 4 MeV electrons to fluences of 10¹⁵ - 10¹⁶ cm^-2 was found to give rise the following radiation defect levels of acceptor nature: E_c- 0.13 eV and E_c-0.2 eV attributed to the complexes V-O₃ and C_sO_i-C_s, as well as E_c-0.35 eV that related with a complex of C, O, and vacancy. The studies of influence of isochronal annealing on properties of these radiation defects have shown their thermal stability till temperature of 500 degrees Celsius. On the basis of obtained results the thermo-radiation approach is proposed for modification of characteristics of silicon p⁺-n structures, which is of important for regulation of thermal stability of recombination parameters of diodes together with increasing of their yield by 5 - 6%.

Using the controlled Malter effect the study was carried out on the application of ITO type oxide layers (In₂O₃-Sn, SnO₂-Sb, 10 nm and 200 nm) deposited onto a glass substrate as a relatively stable electron emitter. The polarizing voltage U_pol has been applied to the field electrode. The investigations were performed in the vacuum of the order 10^-6Pa. As a result of applying U_pol and illumination, electrons and photoelectrons are released and enter electron multiplier. The electrons create voltage pulses in the multiplier which are recorded in the multichannel pulse amplitude analyzer. The amplitude spectra N(U) equals f(U) were measured for unilluminated samples and illuminated by a quartz lamp. The exponential dependence of the pulse frequency n equals f(U_pol) has been found. It was also found that additional effect at simultaneous emission of two electrons (DPE - double photoelectron emission) as result of absorption of a single photon have to be taken into account. Using the retarding field method was evaluated that the emitted electron energy (in dark and under illumination) can achieve even 50 eV, but most of the electrons (about 80%) have energies from hear zero up to 10 eV. Photoinduced optical phenomena in glass-ITO system are studied using experimental spectroscopic and theoretical quantum chemical methods. Photoinduced optical second harmonic (SHG) has been also observed in these films. Theoretical calculations have shown that SnO₄ tetrahedral interacting with SiO₄ clusters of the glass substrate play central role in observed nonlinear photoinduced changes.

Yield control in manufacturing of microelectronic devices is closely related to defect control and contamination control. For a proper definition of process windows, e.g. maximum sit time or minimum quality of used process materials, the impact of different kinds of contamination on device performance has to be determined. This paper describes the outline of a strategy that was used for an estimation of the impact of organic airborne molecular contamination (AMC) on a realistic device process on the basis of selected experimental results: A manufacturing process was performed using intentionally contaminated substrates, monitoring measures were installed and baseline-levels were determined, time-dependent effects were detected, and process windows were defined on the basis of calculations. A gate-oxide integrity test was performed using intentionally contaminated silicon wafers. Contamination was performed via the gas phase using individual organic compounds. This test indicates that, besides the overall concentration of organic airborne molecular contamination, also the additional presence of small amounts of individual organic compounds has an effect on gate-oxide quality. The installation of measures for the monitoring of organic contamination using Gas-Chromatography/Mass-Spectrometry (GC/MS) or Time-of-Flight -- Secondary-Ion-Mass-Spectrometry (ToF-SIMS) lead to the observation that the deposition of organic contamination onto wafer surfaces can be a very fast process. Especially the preparation of blank samples is a procedure which is complicated by this effect. For an adequate definition of process windows it is necessary to estimate the time that remains until a freshly cleaned wafer is covered by a monolayer or organic contamination. This estimation was made on the basis of calculations using gas kinetic theory. Under standard cleanroom conditions the calculated time is in the range of minutes and is strongly depending on the adsorption probability of individual organic compounds and their individual concentrations.

Advanced process control (APC) techniques become more and more important as short innovation cycles in microelectronics and a highly competitive market requires cost-effective solutions in semiconductor manufacturing. APC marks a paradigm shift from statistically based techniques (SPC) using monitor wafers for sampling measurement data towards product wafer control. The APC functionalities including run-to-run control, fault detection, and fault analysis allow to detect process drifts and excursions at an early stage and to minimize the number of misprocessed wafers. APC is being established as part of factory control systems through the definition of an APC framework. A precondition for APC is the availability of sensors and measurement methods providing the necessary wafer data. This paper discusses integrated metrology as an enabler for APC and demonstrates practical implementations in semiconductor manufacturing.