Relaxing LER requirement in EUV lithography

Yandong Luo; Puneet Gupta

doi:10.1117/12.2297515

20 March 2018 Relaxing LER requirement in EUV lithography

Yandong Luo, Puneet Gupta

Proceedings Volume 10588, Design-Process-Technology Co-optimization for Manufacturability XII; 105880O (2018) https://doi.org/10.1117/12.2297515
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

Low throughput has been a critical issue in extreme ultraviolet (EUV) patterning due to the difficulty in increasing light source power. This limitation has driven the need for photoresists with better throughput which unfortunately come with higher line edge roughness (LER). In this work, the possibility of relaxing LER requirements for metal layer patterned by EUV lithography (EUVL) is studied. Single patterning and litho-etch litho-etch (LELE) patterning with EUVL are considered. To assess the impact of LER on design yield, analytical and simulation based modeling approaches are developed, which consider the LER induced metal wire shorts/opens and the enhanced time dependent dielectrics breakdown (TDDB) for metal wires with different geometries. The impact of LER on wire delay is studied by Elmore’s delay model.

Citation Download Citation

Yandong Luo and Puneet Gupta "Relaxing LER requirement in EUV lithography", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880O (20 March 2018); https://doi.org/10.1117/12.2297515

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