Extending materials to systems co-optimizationTM (MSCOTM) modeling to memory array simulation

Ashish Pal; Plamen Asenov; El Mehdi Bazizi; Jaehyun Lee; Benjamin Colombeau; Sanjay Natarajan; Blessy Alexander; Buvna Ayyagari-Sangmalli; Victor Moroz; Xi-Wei Lin

doi:10.1117/12.2583923

22 February 2021 Extending materials to systems co-optimization^TM (MSCO^TM) modeling to memory array simulation

Ashish Pal, Plamen Asenov, El Mehdi Bazizi, Jaehyun Lee, Benjamin Colombeau, Sanjay Natarajan, Blessy Alexander, Buvna Ayyagari-Sangmalli, Victor Moroz, Xi-Wei Lin

Author Affiliations +

Proceedings Volume 11614, Design-Process-Technology Co-optimization XV; 116140G (2021) https://doi.org/10.1117/12.2583923
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

In this paper, we describe a framework to enable the memory array simulations for Materials to Systems Cooptimization^TM (MSCO^TM) flows. The methodology is applied for projected 3 nm logic FinFET technology node SRAM array. To form the SRAM array, a “tiling” approach is utilized, where neighbor cells are created by copying and mirroring the first cell. Then this process is repeated to create the rest of the array. Electrical pulses are applied to the word-line and bit-line to activate the read and write operations. We demonstrate 128 ×128 SRAM array simulations and find that the farthest cell from the word-line driver is vulnerable.

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Ashish Pal, Plamen Asenov, El Mehdi Bazizi, Jaehyun Lee, Benjamin Colombeau, Sanjay Natarajan, Blessy Alexander, Buvna Ayyagari-Sangmalli, Victor Moroz, and Xi-Wei Lin "Extending materials to systems co-optimization^TM (MSCO^TM) modeling to memory array simulation", Proc. SPIE 11614, Design-Process-Technology Co-optimization XV, 116140G (22 February 2021); https://doi.org/10.1117/12.2583923

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