Presentation + Paper
28 April 2023 System-level evaluation of 3D power delivery network at 2nm node
Giuliano Sisto, Rongmei Chen, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
Author Affiliations +
Abstract
Fine-pitch 3D integration is considered a promising way to advance traditional CMOS scaling as 3D interconnects are currently capable to match the connectivity among functional sub-blocks of a system, enabling their displacement on different tiers. A major bottleneck for 3D ICs is represented by the power delivery, due to the challenge of supplying multiple dies. This work aims to provide insights into the system-level impact of PDN in a 3D chip, in terms of frequency and IR drop. A highly-interconnected memory-dominated SoC is physically implemented using the same 2nm technology in 2D and 3D. For both options, the results are compared with an ideal PDN-less implementation, showing that 3D-induced frequency (up to 9.3%) and wirelength (∼ 10%) benefits are retained upon PDN insertion. From the power integrity perspective, a ∼ 60mV dynamic IR drop improvement is observed in 3D, compared to a conventional frontside PDN in 2D, when considering the 90th percentile of a cumulative distribution function. This work validates the expected technology-driven benefits of 3D integration at the system physical design level, in a realistic environment including a 3D PDN.
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Giuliano Sisto, Rongmei Chen, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, and Julien Ryckaert "System-level evaluation of 3D power delivery network at 2nm node", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950Y (28 April 2023); https://doi.org/10.1117/12.2656469
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KEYWORDS
Metals

3D acquisition

Design and modelling

Wafer bonding

Back end of line

Dysprosium

Semiconducting wafers

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