Paper
1 July 1991 Effects of wafer cooling characteristics after post-exposure bake on critical dimensions
Teresa L. Lauck, Masafumi Nomura, Tsutae Omori, Kazutoshi Yoshioka
Author Affiliations +
Abstract
VLSI design rules require existing LSI design rules to extend to sub-micron and half-micron geometries. Using high resolution resist and 5X stepper (G- line) technology along with a Post-Exposure Bake (PEB) is a common method to improve the resolution. The PEB drives out residual photoresist solvents which can interfere with the develop process, resulting in CD variations. PEB strongly influences CD variations. The authors consider the following PEB parameters in this CD improvement study: (1) altering the PEB temperature, (2) altering the PEB time, and (3) altering the queuing time between PEB and cool prior to develop. The process characterization data includes critical dimension data for 0.8 micrometers lines, including proximity effects data on four high-resolution photoresists.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Teresa L. Lauck, Masafumi Nomura, Tsutae Omori, and Kazutoshi Yoshioka "Effects of wafer cooling characteristics after post-exposure bake on critical dimensions", Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); https://doi.org/10.1117/12.44463
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Cited by 1 scholarly publication.
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KEYWORDS
Semiconducting wafers

Photoresist materials

Inspection

Integrated circuits

Process control

Metrology

Critical dimension metrology

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