Device performance and optimization for 5th- and 6th-generation microprocessors

Bijnan Bandyopadhyay; Jon Cheek; Robert Dawson; Michael Duane; Jim Fulford; Mark I. Gardner; Fred N. Hause; Bernard Ho; Daniel Kadoch; Raymond Lee; Ming-Yin Hao; Chuck May; Mark Michael; Brad Moore; Deepak Nayak; John L. Nistler; Dirk Wristers

doi:10.1117/12.284617

27 August 1997 Device performance and optimization for 5th- and 6th-generation microprocessors

Bijnan Bandyopadhyay, Jon Cheek, Robert Dawson, Michael Duane, Jim Fulford, Mark I. Gardner, Fred N. Hause, Bernard Ho, Daniel Kadoch, Raymond Lee, Ming-Yin Hao, Chuck May, Mark Michael, Brad Moore, Deepak Nayak, John L. Nistler, Dirk Wristers

Author Affiliations +

Proceedings Volume 3212, Microelectronic Device Technology; (1997) https://doi.org/10.1117/12.284617
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.

Citation Download Citation

Bijnan Bandyopadhyay, Jon Cheek, Robert Dawson, Michael Duane, Jim Fulford, Mark I. Gardner, Fred N. Hause, Bernard Ho, Daniel Kadoch, Raymond Lee, Ming-Yin Hao, Chuck May, Mark Michael, Brad Moore, Deepak Nayak, John L. Nistler, and Dirk Wristers "Device performance and optimization for 5th- and 6th-generation microprocessors", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284617

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