Paper
16 July 2002 Overlay tool comparison for sub-130-nm technologies
Beth Russo, Michael Bishop, David C. Benoit, Richard M. Silver
Author Affiliations +
Abstract
The Overlay Metrology Advisory Group (OMAG), which includes representatives from International SEMATECH Member Companies and the National Institute of Standards and Technology, has collaborated to create a unified specification for overlay measurement tools [1]. The methodology and results of an overlay benchmarking comparison of several tools are discussed in this paper. As device technologies shrink below the sub-130nm range, a critical need arises to develop more precise tools to measure overlay. Overlay metrology capability needs to be available for detecting and controlling total device overlay regardless of the source of error. The misregistration measurement uncertainty introduced by the overlay tool can be compared for several systems. A benchmarking study is currently underway and focuses on the existing technique of optical measurement of centerline offsets in different target designs. The critical parameters that the study analyzes include precision, accuracy, throughput, through focus measurements, and recipe portability. Imaging issues such as low contrast targets, across wafer thickness variation, CMP effects, and grainy metal targets can contribute greatly to overlay errors. Several process stacks were designed to incorporate some of these imaging issues and test the limitations of the overlay tools. The same set of wafers and test locations were measured at each supplier site and the results were analyzed. This paper focuses on the methodology used for overlay benchmarking and examples of the results generated with respect to the parameters tested.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Beth Russo, Michael Bishop, David C. Benoit, and Richard M. Silver "Overlay tool comparison for sub-130-nm technologies", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473464
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Semiconducting wafers

Overlay metrology

Silicon

Chemical mechanical planarization

Data modeling

Time metrology

Calibration

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