Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Stewart A. Robertson; Doris Kang; Steven D. Tye; Steven G. Hansen; Anita Fumar-Pici; Tsann-Bim Chiou; Jeff D. Byers; Chris A. Mack; Mark D. Smith

doi:10.1117/12.474170

24 July 2002 Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Stewart A. Robertson, Doris Kang, Steven D. Tye, Steven G. Hansen, Anita Fumar-Pici, Tsann-Bim Chiou, Jeff D. Byers, Chris A. Mack, Mark D. Smith

Author Affiliations +

Proceedings Volume 4690, Advances in Resist Technology and Processing XIX; (2002) https://doi.org/10.1117/12.474170
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

In this work an automate optimization routine is used to modify modeling parameters for a chemically amplified photoresist, with the goal of minimizing the error observed between lithography simulation and experimental results. It is shown that a basic tuning procedure modifying, optimizing only CD measurement offset and acid generation efficiency, improves the fit significantly. Further improvements can be made by optimization of the diffusion-deprotection kinetic parameters, in combination with the two aforementioned values. It is shown further improvement is observed if the actual temperature profile experienced in the postexposure bake process is considered and the temperature dependence of both the diffusion and the deprotection processes are optimized. This parameter values that result in this improvement infer a temporal offset in the start, and finish, of deprotection and acid diffusion.

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Stewart A. Robertson, Doris Kang, Steven D. Tye, Steven G. Hansen, Anita Fumar-Pici, Tsann-Bim Chiou, Jeff D. Byers, Chris A. Mack, and Mark D. Smith "Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history", Proc. SPIE 4690, Advances in Resist Technology and Processing XIX, (24 July 2002); https://doi.org/10.1117/12.474170

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