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There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask
facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of
situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely
with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both
technology development and benefited from corporations. Our involvement in manufacturing is driven by the following
three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable
design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been
involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The
second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to
market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough
visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been
observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To
achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity
has to be monitored.
Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial
development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges
for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time
(TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that
assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a
need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design
criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask
manufacturing has contributed significantly to our success in past many nodes and will continue.
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