Mr. Toshiyuki Hisamura Profile

Toshiyuki Hisamura

Principal Member of Technical Staff at AMD

SPIE Involvement:

Author

Proceedings Article | 26 May 2022 Presentation + Paper

EUV and immersion lithography integration in 7nm FPGA production

Qi Lin, Nui Chong, Toshiyuki Hisamura, Jonathan Chang

Proceedings Volume 12051, 120510G (2022) https://doi.org/10.1117/12.2614366

KEYWORDS: Extreme ultraviolet, Photomasks, Semiconducting wafers, Metals, Extreme ultraviolet lithography, Optical lithography, Critical dimension metrology, Immersion lithography, Resistance, Field programmable gate arrays

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Proceedings Article | 22 February 2021 Presentation + Paper

Optimization of the EUV contact layer process for 7nm FPGA production

Qi Lin, Toshiyuki Hisamura, Nui Chong, Jonathan Chang

Proceedings Volume 11609, 116090V (2021) https://doi.org/10.1117/12.2584288

KEYWORDS: Extreme ultraviolet, Field programmable gate arrays, Resistance, Extreme ultraviolet lithography, Transistors, Immersion lithography

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Proceedings Article | 23 March 2020 Presentation + Paper

Improvement of SADP CD control in 7nm BEOL application

Qi Lin, Toshiyuki Hisamura, Nui Chong, Jonathan Chang

Proceedings Volume 11327, 113270X (2020) https://doi.org/10.1117/12.2552168

KEYWORDS: Metals, Critical dimension metrology, Semiconducting wafers, Silicon, Resistance, Etching, Back end of line, Photomasks, Double patterning technology, Lithography

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Proceedings Article | 16 September 2014 Paper

Double-patterning optimization in 20nm SRAM design

Qi Lin, Toshiyuki Hisamura, Nui Chong, Hans Pan, Yun Wu, Jonathan Chang, Xin Wu

Proceedings Volume 9235, 923505 (2014) https://doi.org/10.1117/12.2066262

KEYWORDS: Double patterning technology, Diffusion, Photomasks, Optical proximity correction, Critical dimension metrology, Silicon, Field programmable gate arrays, Semiconducting wafers, Optical lithography, Optical alignment

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Proceedings Article | 23 September 2009 Paper

Fabless company mask technology approach: fabless but not fab-careless

Toshiyuki Hisamura, Xin Wu

Proceedings Volume 7488, 748821 (2009) https://doi.org/10.1117/12.833505

KEYWORDS: Photomasks, Semiconducting wafers, Manufacturing, Field programmable gate arrays, Air contamination, Failure analysis, Mask making, Critical dimension metrology, Resolution enhancement technologies

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There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both technology development and benefited from corporations. Our involvement in manufacturing is driven by the following three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity has to be monitored. Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time (TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask manufacturing has contributed significantly to our success in past many nodes and will continue.

Conference Committee Involvement (2)

Optical Lithography XXXIV

22 February 2021 | Online Only, California, United States

Optical Microlithography XXXIII

25 February 2020 | San Jose, California, United States

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