Stack and topography verification as an enabler for computational metrology target design

Michael E. Adel; Inna Tarshish-Shapir; David Gready; Mark Ghinovker; Chen Dror; Stephane Godny

doi:10.1117/12.2086084

10 April 2015 Stack and topography verification as an enabler for computational metrology target design

Michael E. Adel, Inna Tarshish-Shapir, David Gready, Mark Ghinovker, Chen Dror, Stephane Godny

Proceedings Volume 9424, Metrology, Inspection, and Process Control for Microlithography XXIX; 94240D (2015) https://doi.org/10.1117/12.2086084
Event: SPIE Advanced Lithography, 2015, San Jose, California, United States

Abstract

Computational metrology target design requires both an accurate metrology simulation engine and an accurate geometric model. This paper deals with the later. Optical critical dimension metrology and cross-section SEM are demonstrated as two useful methods of geometric model verification with differing capabilities. Specifically, a methodology is proposed which allows the metrology engineer to quantify the level of accuracy required by the model as a function of the tolerable uncertainty in the prediction of metrology performance metrics. The methodology identifies a subset of model parameters which need to be verified enabling the metrology engineer to invest the minimum effort in stack and topography verification which will lead to performing target designs on the first design round.

Citation Download Citation

Michael E. Adel, Inna Tarshish-Shapir, David Gready, Mark Ghinovker, Chen Dror, and Stephane Godny "Stack and topography verification as an enabler for computational metrology target design", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94240D (10 April 2015); https://doi.org/10.1117/12.2086084

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KEYWORDS

Metrology

Diffraction gratings

Scanning electron microscopy

Overlay metrology

Uncertainty analysis

Diffraction

Performance modeling

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