New era of logic technology evolution: Z-dimensional scaling

Dechao Guo

doi:10.1117/12.2623261

13 June 2022 New era of logic technology evolution: Z-dimensional scaling

Dechao Guo

Proceedings Volume PC12056, Advanced Etch Technology and Process Integration for Nanopatterning XI; PC1205601 (2022) https://doi.org/10.1117/12.2623261
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States

Abstract

Over last five decades, transistor physical scaling has been the primary enabler for semiconductor technology evolution. Benefit of scaling in transistor gate contact pitches and metal pitches translates into benefits at the circuit level, and the chip level. As the transistor scaling gets close to its scaling limit due to short channel effect and process limits, new forms of scaling emerge to further extend technology evolution. The talk will focus on Z-dimensional scaling as the driver for new era of logic technology evaluation. Z-dimensional scaling is featured with innovations beyond traditional technology scaling. It includes innovations at the transistor level by stacking, the interconnect and power distribution level by their re-arrangement at both sides of the transistors, and the packaging level by heterogenous integration. Vertically integrating these innovations opens a new domain for technology and product evolution for next several decades.

Conference Presentation

Citation Download Citation

Dechao Guo "New era of logic technology evolution: Z-dimensional scaling", Proc. SPIE PC12056, Advanced Etch Technology and Process Integration for Nanopatterning XI, PC1205601 (13 June 2022); https://doi.org/10.1117/12.2623261

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